Stratix 10 SX FPGA Level 4 Slave Peripheral Bus Control Configuration

[Hans_1st]

Hello All,

Thanks for reading my problem!

I am working on controlling UART1 in Intel Stratix 10 SX SoC Development Kit output something. I use SignalTap II to simulate and the result is that the output data is in loop of UART1 block register(0xFFC02114), which means UART1 does not do anything after data is received by the UART1 control register.

I meet the same situation on Cyclone V SoC Development Kit. The way I solve this problem is to configure the register named "l4_sp(0xFF800000)". If I set bit 4 in this register, the Lightweight HPS to FPGA AXI bridge is enabled in the main user space so I can access the FPGA memory space through the bus. I am trying to use the same way on Intel Stratix 10 SX SoC Development Kit, but the difference between these two development kits is that Intel Stratix 10 SX SoC Development Kit has secure firewalls. I find I need to configure the bit  0, 8, 16, 24 of L4_PER Security Control Registers (SCR)-noc_fw_l4_per_l4_per_scr(0xFFD21070) to allow the secure and non-secure transactions for UART1, but this register must be configured within "SECURE | PRIVILEGEMODE" access mode. 

Could anyone please show me how I can configure this register, or some other ways I can achieve the same goal?

Thanks very much.

PS: I try to configure this register in "u-boot.scr" file like what I see in RocketBoards(https://rocketboards.org/foswiki/Documentation/S10SoCBridgeConfiguration), but I does not work.

[Hans_1st]

Anyone know this？

[EricMunYew_C_Intel]

You can modify the security control register by referring to below.

https://rocketboards.org/foswiki/Documentation/BuildingBootloader#Appendix:_Managing_Secure_L3_Registers_on_Stratix_10_44_Agilex_and_N5X

[Hans_1st]

Thanks for replying！

I checked this web and I had some questions want to ask:

(1) Is this Appendix only based on using ATF (Arm Trusted Firmware) as the Secure Monitor or not? Because EL3 is only generated by building Arm Trusted Firmware.

(2) If I want to use U-Boot as the Secure Monitor (non-ATF way) to control UART1 on L4 Slave Peripheral Bus, I know I can manage/configure secure L3 or L4 registers in "u-boot.scr" file. So how many and what kind of registers should I manage/configure to achieve my goal?

[EricMunYew_C_Intel]

1. Yes it is for U boot with ATF. 

2. We no longer support issue with non-ATF flow. You may refer to below.

https://rocketboards.org/foswiki/Documentation/RemoteSystemUpdateCompatibility

[Hans_1st]

I build a new community which shows more information about this problem on https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/How-to-Read-Write-L4-Peripheral-Slave-Bus-on-S10-SX-Device/td-p/1364632. 

Anyone who knows how to solve this problem, please let me know.

Best Regards,

Hans_1st

[EricMunYew_C_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.