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HBhat2-GRL
New Contributor I
523 Views

Stratix 10 SoC Dev Kit - L-tile - FPGA-DDR4 (SODIMM ) Example design

Hi,

I am using stratix 10 SoC dev kit

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/strati...

I have downloaded the BTS (Board Test System) and checked all the interfaces. But, I see that in the BTS, there is no binary for FPGA-DDR4 (SODIMM, 16GB) interface[BTS has the binary to validate HPS DDR4 memory] .  I tried with example project, but DDR4 SODIMM Calibration done is not observed. 

Can anyone share the exact project to validate the  FPGA-DDR4 (SODIMM, 16GB)  interface.

With Regards,

HPB

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10 Replies
ybin
Employee
498 Views

Hello,

Normally, there is one UDIMM memory in Stratix10 Devkit, not SODIMM. You mean that you just got SODIMM, not UDIMM, is that right? BTW, where do got the Devkit, from Intel side or agent?

HBhat2-GRL
New Contributor I
494 Views

Hi,

As per stratix 10 SoC product page (below link) & user guide, it is mentioned as SODIMM (attached the snapsot)

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/strati...

 

 

We got it from Intel's authorized distribution channel here in India (Cytech).

 

With Regards,

HPB

 

HBhat2-GRL
New Contributor I
478 Views

Hi,

Anybody has the FPGA-DDR4 (16GB) design for Stratix 10 SoC dev kit?

With regards,

HPB

ybin
Employee
472 Views

Hi,

You need to download package installer from below page, and then you can find the design locates in download zip file. It locates in examples/sodimm_ddr4 folder.

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/strati...

 
 
 
 

 

HBhat2-GRL
New Contributor I
469 Views

Hi,

Yes, I have downloaded the package & tried to create the project as mentioned in the readme file.

I ran the below command in command prompt & I am getting the error message while creating the project

quartus_sh -t make_qii_design.tcl

------------------------------------------------------------------------------------------------

Error (23035): Tcl error: child process exited abnormally
while executing
"exec -ignorestderr $qsys_generate_exe_path $qsys_file --pro --synthesis --family=$family --part=$device >>& ip_generate.out"
(file "make_qii_design.tcl" line 98)
------------------------------------------------
child process exited abnormally
while executing
"exec -ignorestderr $qsys_generate_exe_path $qsys_file --pro --synthesis --family=$family --part=$device >>& ip_generate.out"
(file "make_qii_design.tcl" line 98)
------------------------------------------------
Error (23031): Evaluation of Tcl script make_qii_design.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 2 errors, 0 warnings
Error: Peak virtual memory: 4871 megabytes
Error: Processing ended: Tue Aug 25 09:59:37 2020
Error: Elapsed time: 00:00:23

------------------------------------------------------------------------------------------

I am using Quartus pro 18.1 & licensed for stratix 10 device.

With regards,

HPB

ybin
Employee
460 Views

Hi,

I can reproduce this error. You can refer to below link to generate a example design based on the emif component in ed_synth.qsys locate in emif_s10_0_example_design folder.

https://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20120.pdf

HBhat2-GRL
New Contributor I
457 Views

Hi,

Thanks for reproducing the problem & it will be great if Intel supports how to solve this.

Regarding the example design, I have done something similar as mentioned in the "External Memory Interfaces Intel® Stratix® 10 FPGA IP Design Example User Guide". However, I will once again correlate between this document & my design  & keep you posted.

Wit Regards,

HPB

ybin
Employee
416 Views

 

I'm glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

bradgiordano
Beginner
353 Views

I wanted to check with you to see if the Intel Stratix-10 SOC Dev Kit can be upgraded from 16GB to 32GB of DDR4 FPGA memory. 

HBhat2-GRL
New Contributor I
290 Views

Hi,

I followed the same procedure & tried to test the interface. Calibration is failing. I have attached the QAR file. Can anybody check the EMIF memory controller settings & point out what went wroung?

Quartus tool used: 18.1

Stratix 10:
FPGA DDR4 part number : MTA18ASF2G72HZ-2G3B1ZG
https://www.digikey.in/htmldatasheets/production/1959037/0/0/1/MTA18ASF2G72HZ.pdf
2400MT/s, CK/CK# freq :1200MHz,
CL = 17, tRCD = 17, tRP = 17
PLL ref clk: 100MHz or 166.66MHz (as per Platform designer recommendation)

 

With Regards,

HPB

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