Stratix 4 Developer Board - Topside RAM too many adress input pins

[Altera_Forum]

I am currently working on a Stratix 4 RAM project but now i got a problem concerning the pins of the RAM. 

The Stratix 4 dev board features a Micron mt41j64m16la-15e (https://www.micron.com/parts/dram/ddr3-sdram/mt41j64m16jt-15e) with 128mb. In the reference manual (https://www.google.de/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&uact=8&ved=0ahukewjihl72x7hoahxdimakhyihcieqfggymae&url=https%3a%2f%2fwww.altera.com%2fcontent%2fdam%2faltera-www%2fglobal%2fen_us%2fpdfs%2fliterature%2fmanual%2frm_sivgx_fpga_dev_board.pdf&usg=afqjcnfr7kodjfkxl0u9rgy87jh-b1vedg) of the board, 15(A14 to A0) pins are listed to be the adress bus of the RAM. However, in the RAM's data sheet says, that the RAM has got only a 14(A13 to A0) pin adress bus. Is there a mistake in the boards Reference Manual or is the datasheet which i use the wrong one? If it is the wrong one, where could i find old Micron datasheets?  Thx for Help,  Siggy

[Altera_Forum]

I don't know if this is the case with your board, but the LSB is often left off the address bus. If the chip outputs 16 bits of data the LSB of the address isn't needed.

[Altera_Forum]

Thanks for the reply  

but if this would be the case, wouldn't there be a pin less at the FPGA and one more at the RAM? I linked the manuals in my original questions. Maybe you see what i mean. Plus I need the distinct location of pin A10 for the initialisation sequence. If the location is somehow influenced by the 15-14 pin issue, i can't control the RAM.

[Altera_Forum]

Now I found the solution. On Page 2-51 of the developer boards Reference Manual it says: 'The DDR3 top port consists of a single DDR3 devices, providing 128 Mbyte with a 

16-bit data bus. The board supports addressing for up to 4 times the memory if larger devices become available.' So the additional pin is for a bigger device and i can ignore it, because at the moment, it is not connected.

[Altera_Forum]

You need to ignore the top two address pins. The least significant address bit isn't wired to the chip in a 16 bit data bus situation like on this board. The address bus represents a byte address. The 16 bit data bus presents two bytes at a time. The two extra bits are needed to address 4x the memory if it is available. 

 The least significant address bit goes from the CPU to the memory controller IP. The memory controller uses it to select the high or low byte from the data bus to present to the CPU when it requests a byte. The output to the memory chip addresses pairs of bytes.