Re: Stratix II GX PCIe Error: Tcl error: can't find package ::ddr::settings

Altera_Forum · ‎02-12-2009

I am trying to compile the Stratix II GX PCIe reference design.

C:\altera\80\kits\stratixIIGX_2sgx90_pcie\examples\DDR2_to_PCIe_ExDsgn

It's the Quartus 8.0 version of the device kit software installed in the default location. Has anyone else seen this problem?

Thanks.

Error: Tcl error: can't find package ::ddr::settings
    while executing
"package require ::ddr::settings"
    (file "verify_timing_for_ddr_ctrl.tcl" line 54)
    invoked from within
"source verify_timing_for_ddr_ctrl.tcl"
    (file "auto_verify_ddr_timing.tcl" line 11)
Error: Evaluation of Tcl script auto_verify_ddr_timing.tcl unsuccessful
Error: Quartus II Shell was unsuccessful. 2 errors, 0 warnings
	Error: Peak virtual memory: 60 megabytes
	Error: Processing ended: Wed Feb 11 18:56:22 2009
	Error: Elapsed time: 00:00:01
	Error: Total CPU time (on all processors): 00:00:00
Error: Quartus II Full Compilation was unsuccessful. 4 errors, 1527 warnings

Altera_Forum · ‎02-12-2009

Can you regenerate the DDR2 core? Just open it with the Megawizard? I think a library path to the DDR2 megafunction may be off. Just a guess. (And yes, if you installed it to the default that shouldn't be a problem, but I think that should work...)

Altera_Forum · ‎02-12-2009

:)

--- Quote Start ---

Can you regenerate the DDR2 core? Just open it with the Megawizard? I think a library path to the DDR2 megafunction may be off. Just a guess. (And yes, if you installed it to the default that shouldn't be a problem, but I think that should work...)

--- Quote End ---

YES! Thanks.

but a new error, see below.

I clicked on |pcie_ddr|ddr_pll_stratixii:g_stratixpll_ddr_pll_inst in the Project Navigator Pane to bring up the Megawizard. The DDR function was still pointing to the v7.1 megafunction, just as you said.

The design kit documentation said the design had been recompiled in 8.0. I'm guessing that the guy/gal who did the recompile still had 7.1 installed too.

edit, a few minutes later...

the same goes for the other ip in the design.

yet another edit...

new error:

Info: Found 2 design units, including 1 entities, in source file auk_ddr_controller.vhd
	Info: Found design unit 1: auk_ddr_controller-rtl
	Info: Found entity 1: auk_ddr_controller
Error (10481): VHDL Use Clause error at auk_ddr_controller.vhd(35): design library "auk_ddr_lib" does not contain primary unit "auk_ddr_functions"
Error (10800): VHDL error at auk_ddr_controller.vhd(35): selected name in use clause is not an expanded name