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Stratix II GX PCIe differential clock assignment

Altera_Forum
Honored Contributor I
1,173 Views

I am a newbee to the world of fpga. I have a stratix II gx pice board. I would like to use the 156.25 MHz clock, named as Osc B. 

 

The development board manual defines the clock as differential  

156.25 MHz xaui_refclk_cn X3 Stratix II GX pin H8 (REFCLK0_B13n) 

xaui_refclk_cp Stratix II GX pin H7 (REFCLK0_B13p) 

 

My question is when I map the clock pins clkp and clkn of the top module to these two pins in quartus 8 in assignment editor, the tool does not recognize pins H8/H7 as differential.  

 

Is there something really basic I am missing? 

 

Further what would be the name of the single ended clock assuming a differential clock buffer is placed next to the two pins? I did not find any differential clock buffer in the mega wizard. 

 

Thanks, 

Fasahat
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5 Replies
Altera_Forum
Honored Contributor I
116 Views

A single signal must represent the differential clock in the top module port (the same with clock outputs and PCIe signals, BTW). The differential I/O standard has to be assigned in Pin Planner or Assignment Editor. As you are using the PCIe Development Kit, didn't you get reference designs with correct pin assignments shipped with the board?

Altera_Forum
Honored Contributor I
116 Views

Closing the thread.  

 

The Differential clock (n part ) is automatically assigned in pin planner, once you assign the positive pin and this signal is the one ready to use. I was under the impression that you need a differential to single ended translation and a new signal name like in xilinx, but it's quite simple here in Altera.
Altera_Forum
Honored Contributor I
116 Views

Hm I have a similar problem with accessing the High-Speed Oscillator 156.25 Mhz on the Stratix II PCIe Devkit board. If i want to assign the H7 (pin in the manual) to the clocksignal in my design, and compile the design i see at the RTL-Viewer that the clocksignal it is stuck at GND. So my component doesn't get a beat. 

 

For I/O Standard I use 1.5-V PCML, at using all the other standards the compilation fails. 

 

can i use this clock in normal design or only in gxbs ? and which settings do I need for using it (the devkit manual doesnt mention it). Do I need an PLL or can I connect it directly ? The other oscillators 25 MHz and 100 MHz I can use normaly with LVDS as IO-Standard. 

 

If I use LVDS in as I/O Standard the following exception occurs at compilation: 

 

Error: Can't place IO "clock_highres" in GXB Ref Clock Pin_H7 because the IO does not have a differential IO standard, or correct Stratix II GX GXB REFCLK Coupling and Termination setting. 

Info: The supported differential I/O standards are LVDS, Differential LVPECL, 3.3-V PCML, 1.5-V PCML, or 1.2-V PCML. 

Info: The supported Stratix II GX GXB REFCLK coupling and termination settings are "OCT 100 Ohms" and "DC coupling external termination". 

 

Did i miss any point ? 

 

Thank you so far
Altera_Forum
Honored Contributor I
116 Views

According to the Stratix IIGX device handbook,that besides receiver and transmitter PLLs, the refclk input can also feed global and regional clocks. 

 

So the problem should be only related to selecting the correct termination scheme, coupling and IO standard. But I didn't try myself.
Altera_Forum
Honored Contributor I
116 Views

Hi mooresstudent, 

 

 

Did u solve the above problem ,,,,,,,how u did can you explain me,,,,,,,,, 

i also facing same problem........
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