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Stratix III DSP kit Quad Video HSMC

Honored Contributor II

i was having difficulty to connect the test pattern to the video buffer that being connected to 1gb of ddr2 dimm. The problem is the output of the clock video show blank screen. :mad::mad: 


I was able to display the test pattern without using the video buffer? 


Anyone has the reference design to test the ddr2 dimm is working properly or not, cause i have try the official emi_ddr2_siii.zip, but the signal tap didn't give any chances to the value inside. It seem like there is no trigger happen all the time. The compilation of emi_ddr2_siii.zip in EDA netlist was unsucessful due to open core license problem...:mad::mad: 


Anybody could help?Thank you
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