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Altera_Forum
Honored Contributor I
1,688 Views

Stratix III Dev kit ethernet problem

I am using the Stratix III dev kit: 

http://www.altera.com/products/devkits/altera/kit-siii-host.html 

and I have programmed the board with the correct NIOS II standard design. I am able to run all of the sample projects on the NIOS II(hello_world etc.), but I cannot get the simple_socket_server (or the web server) to work. 

 

Compilation and download look fine, but an error is returned when the PHY is initialized. 

 

The message returned in the IDE looks like this: 

 

Your Ethernet MAC address is 00:07:ed:ff:f6:fe 

prepped 1 interface, initializing... 

[tse_mac_init] 

INFO : TSE MAC 0 found at address 0x00001400 

ERROR : MAC Group[0] - No PHY connected! 

ERROR : PHY[0.0] - No PHY connected! Speed = 100, Duplex = Full 

OK, x=161, CMD_CONFIG=0x00000000 

 

On the board, both the Tx and Rx LEDs are off, and the hub that I am plugged into also does not indicate a connection. 

 

I reinstalled the Dev kit software, as well as the hardware .sof file to verify that I had not inadvertantly messed anything up, but the problem is still present. 

 

Does anyone have any ideas or pointers on how to debug this? 

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11 Replies
Altera_Forum
Honored Contributor I
86 Views

Hello, 

I have had the same problem, somebody on this discussion sended me this project for stratix III DSP dev.kit and after this it works. (simple socket server and web server too), but not in uClinux... 

 

Good luck Jan 

 

From project i deleted some rpt file, it was too long.
Altera_Forum
Honored Contributor I
86 Views

I too am experiencing the exact problem as djw posted. I too am using the V8.0 Stratix III dev kit with the example "standard" design for the SIII board. I wonder if v9.0 would fix it, but there doesn't seem to be anywhere to download it. 

 

I have downloaded the example that naceradsky posted, and while that does work, it is not really clear what has been done there to fix it. While it works, it doesn't really help me for creating my own design. The DOC file describes how the NIOS project was changed, but there have also been changes to the Quartus/SOPC side of things.  

 

Googling has drawn a big blank (apart from this thread). Would some kind person be able to point me in the direction of information on what the issue is here and how to fix it?
Altera_Forum
Honored Contributor I
86 Views

Hi all, 

no need to say that I'm experiencing the same too. I'm playing a webserver example application. Thanks very much to naceradsky, you project seems to work fine, at least until I don't generate system and compile by myself. When I do, I have a problem and something unexpected (problems are always)... The unexpected is that compilation generates two .sof files the standard one and one called _timelimited.sof or something like this. System ID is not compatible with the one from NIOSIDE with the standard .sof file, have to load the time limited one (I have a full license). Anyway it doesn't desturb me too much but I would have a more clear idea on this point if someone could help me. But let's talk about the problem. When I compile the project by myself everything seems to succeed but no way to reach the development board from the net. MAC configuration messages looks like the working case, "web server starting up" but development board is unreachable. Neither ping can get answers.  

Please, does anyone have a suggestion to me to fix this problem?! 

Thanks a lot guys. 

Regards, Massi.
Altera_Forum
Honored Contributor I
86 Views

Ok, we have made some real progress on this today. We can successfully ping out and in from uClinux on a system using the Altera Triple Speed Ethernet MAC. 

 

I will outline our hard-won knowledge: 

 

First, in the words of one of my colleagues, the reason this is so difficult is that this nice, versatile setup has us "feature f$%*ked". There are simply too many options. We first tried the igor mac with the Opencores mac driver. Everything was going great until we realized that the PHY comes out of reset in Gigabit mode, which we could not get to work(nor did we care...all we wanted was 10/100) Not knowing yet how to go through the MDIO interface to change this (Simply set bits 3:0 in reg 27 of the Marvell Phy to 1111, and then reset the phy), we decided to try to port the working case posted on this thread by naceradsky to uClinux.  

 

I wanted to try the SLS MAC driver with this, but I have never been able to get a kernel to boot with it so...we used the (ominously EXPERIMENTAL) Tripple (sic) Speed Ethernet driver that is the other option for this under uClinux. Note, this is a pretty cut down driver, and it doesn't support interfaces used by mii-tool and eth-tool(direct MII manipulation). Also, it doesn't support MAC Address modification. 

 

So, we begin our next adventure: 

We patterned our system exactly as in naceradsky's example, and were not able to get anywhere. One reason seemed to be too many features: 

The ptf file post by naceradsky, specified a GMII MAC with a PCS. What is a PCS? Apparently it is a phy in and of itself, and requires only a "industry standard" 10 bit interface to an external SERDES to work. Since naceradsky's example works, I can only assume that this PHY can do that, though I have no idea how to make it happen. So, it didn't work for us. One way the problems we had manifested themselves, is that we could not actually read or write to the MDIO interface on the Marvell Phy. This is because, according to the TSE MAC spec, the PCS function is placed at position PHY0 in the MAC, meaning that all MDIO reads are immediately returned on the Avalon bus, because they never actually go to MDIO. Unfortunately, all those reads acted like all MDIO registers were 0. :( 

 

But now, an explanation: The TSE MAC can support up to two phys. Talking to one or the other is done by writing to a separate address space on the MAC. The phy ID, *which in the casre of this board is always 0x12!* is assigned to each space, and is used in all subsequent mdio packets. 

 

Since the ATSE driver (the experimental Tripple Speed Ethernet one), always reads/writes to phy space 0, all reads were going to the PCS, which is communicating with an unconfigured internal phy (apparently).  

 

At that point, we mucked with the MAC driver to access the phy through the phy 1 interface(by telling that interface to reference phy id 0x12, and then reading/writing to the proper MAC address range), and were able to talk to the phy. However, we still could not ping through. We observed the MAC TX FIFO using ClearBlue FPGA, and found that we were driving data into the MAC, but that it wasn't being driven through to the PHY over the GMII interface. 

 

So, we decided to simplify, and we went back to SOPC builder and inserted the standard 10/100/1000 MAC (the one without the PCS). This one is kinda funny, in that it actually creates two whole sets of interface ports, one for GMII (8 bit TX data) and one for MII (4 bit TX data). So, which one to connect? Well, in our case, the correct answer is the MII set (4 bit), and leave the GMII dangling to be optimized away. This, in conjunction with code in the MAC driver to set Phy Register 27 bits 3:0 to 1111b, which sets us to 10/100 MII mode, followed by a software reset by hitting bit 15 of the MAC command register (base + 0x8), FINALLY resulted in a working, 100 Mb, full duplex system under linux. WooHoo! 

 

At this point, you are probably saying "What the...", so let me sum up: 

 

- I am using uClinux (not the new one with MMU support, at least not yet) 

- I am using a modified version of the "Experimental" Tripple(Sic) Speed ethernet MAC 

- I am using the Altera TSE MAC hardware:10/100/1000 Ethernet MAC with 2048 deep FIFOs. 

- I have connected the MII interface to the PHY. This is the 4 bit txd interface. 

- Both clocks are coming from the phy (both 25MHz), so no extra PLLs. 

- I modified the Tripple(sic) speed ethernet mac driver to set the extended status register (MDIO reg 27) on the PHY:bits 3:0 to 1111. And then I reset the phy by writing a 1 to bit 15 of the MAC command register (BASE + 0x8) 

 

I am including 2 files: 

 

The ptf (appended .txt so that this rediculous forum system would allow me to upload the file) 

The top-level interface file 

 

I do not have the atse.c and atse.h available at this moment, but I will post them tomorrow. I just wanted to get this all written down before I forgot any details (of which there are just a couple :) ) 

If you are using this MAC driver, simply drop these files in nios2-linux/linux-2.6/drivers/net, then rebuild. 

 

Have fun!
Altera_Forum
Honored Contributor I
86 Views

Hi djw, 

 

 

--- Quote Start ---  

I do not have the atse.c and atse.h available at this moment, but I will post them tomorrow.  

--- Quote End ---  

 

 

Any chance we could see these? It sounds like you're on the right path of what I need to know, but I'm missing some details... somewhere.
Altera_Forum
Honored Contributor I
86 Views

Hi djw, 

 

any possibility that you post the atse.c and atse.h files ? 

rr.
Altera_Forum
Honored Contributor I
86 Views

Dear All, 

I'm back after a long time. Make the gigabit interface working succeded using the project posted in this thread. Connection is reliable, i can send and receive data. But Unfortunately I experienced a very low data transfer, more or less the same as the 100Mbps link. Negotiation on both side is at 1000. 

Does anyone has some suggestion to understand this, Am I wrong somewhere 

or is there some kind of bug that succeed in 1Gb negotiation but strongly limits the transfer rate?  

Please, help me to understand the problem. 

Thanks a Lot.
Altera_Forum
Honored Contributor I
86 Views

Hello everybody, 

does anyone have a working project for the StratixIII dsp board with the tse driver working on uclinux (including possibly the modified tse driver)?
Altera_Forum
Honored Contributor I
86 Views

i too have same prob;lem and it asks for 8/9 digit serial no 

written on nios dev board.. 

how to get it? 

I have Stratix III dev, kit..
Altera_Forum
Honored Contributor I
86 Views

Does anyone have a functional project for this board that is compatible with Nios II Linux or uClinux? 

 

I just need one that has altera triple speed ethernet and run linux (uClinux or nios2 linux) correctly. 

 

If some of you could send me this project I would really appreciate.  

 

 

Thank you.
Altera_Forum
Honored Contributor I
86 Views

Hi, I need some support with this stratixIII_3sl150_dev_TSE_SGMII_v1.zip project which naceradsky uploaded here. 

 

The connection seems to work fine, but I need to chenge the IP and Gateway data on the project, not on my computer as the documentation says. The problem is that I can't build the executable. I'm working with the NIOS II Eclipse IDE, but the makefile seems not to work with it. I wondered that the makefile is made to work with cygwin or MinGW (which I'm using right now), but I can't compile it because some problems are appearing. 

Does anyone know how to compile it? Or maybe does someone know the creator of the project and the contact to ask him? 

 

Thanks a lot.
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