I inherited this Stratix IV 530 Dev. board which I can not program the CFI FLASH. I am following the guide but there is a mismatch somewhere. When I try to restore the factory recovery setting of the CPLD and CFI the JTAG codes do not agree with the board components. The board is from 2009. Where do get the .sof, .pof for my board? I downloaded the installation kits for the 530 version 10.1 and 11.1 but they don't work.:(Thanks, S.
As far as I can tell there is only one (DK-DEV-4SGX530N) : http://www.altera.com/products/devkits/altera/kit-siv-gx.html#contentsI downloaded the kit installation for this board with the factory recovery files and instructions, etc. I tried using the "restore.sh" and also using NIOS II FLASH programmer. The programmer gave me an error saying that the JTAG IDs of the CPLD and CFI mismatch. I compared the CFI memory map with the 230 version of the board at it is different. The user HW space for the 530 starts at 0x2000000 while the 230 starts at 0xC200000. I wonder if Altera has an archive of configuration files for older boards? although they are still selling them for $5995... Thanks Dave, S.
--- Quote Start --- As far as I can tell there is only one (DK-DEV-4SGX530N) --- Quote End --- There are other boards from other manufacturers, eg., the Terasic DE4. I have this board, but in the 230K version. I've never bothered to use the factory files. What is it you want to get from the factory files? For example, if you want to know that you have a sane setup, I could send you a basic blinky LEDs file. It would be for the 230K design. But if you look at the pin assignments file I send you, you can check whether the assignments are the same on the 530K, or if you are worried about damaging the board, I can take a look tomorrow. If you really want to get the factory recovery files to work, I can try the 230K versions. Cheers, Dave
You are very kind, thanks. I do have a NIOS II design with PCIe core that works fine on the 530 board. Now I want to program the CFI so that it can boot and run on powerup.This is the first time that I am trying to program the CFI of this board and I can't do it. I am following the user guide carefully. I don't quite understand why when I make the .flash I have to have the --offset=0x02000000 and when programming the CFI there I have to use a --base=0x08000000. These numbers don't agree with the memory map table provided above. There is a rotary switch which needs to be turned after programming. I don't care about the factory file, it's just that I can't program my design so I figured I would try the factory recovery files but they don't program either. What CFI address does the FPGA start configuring from? 0x00000000 ? or is it offset by the CPLD and the rotary switch? Can you see if it makes sense to you: sof2flash --input= <yourfile>_hw.sof --output=<yourfile>_hw.flash --offset=0x2000000 --pfl --optionbit=0x00018000 --programmingmode=PS Then, nios2-flash-programmer --base=0x08000000 <yourfile>_hw.flash http://www.altera.com/literature/ug/ug_sivgx_fpga530_dev_kit.pdf Cheers, S.
I'll look at the 230K tomorrow and try reprogramming the flash on that. The procedure should be identical. If the instructions are somehow incorrect, I'll figure out the correct procedure for you and post it here.Cheers, Dave
I've installed the v11.1 files for the 230K and 530K design. The earlier version of the 230K design uses SOPC builder to define the board-update-portal design. If you open the SOPC system, the ext_flash is mapped to 0x0800_0000. That is why the nios2-flash-programmer commands used to communicate with that design use 0x0800_0000 for the flash address.The v11.1 designs use Qsys. If I open the Qsys system for the v11.1 230K or 530K design, the flash (ext_flash) is mapped to address 0 of a pipeline bridge, which is mapped to address 0x0800_0000 in the CPU address map. So, both the old and new design should work with the commands you quoted above from the user guide. I'll update my board and post the results. Cheers, Dave
Thanks Dave. I also found the proper installation for my dev. board by going to all the way back to:ftp://ftp.altera.com/outgoing/devkit/91/stratixive_4se530es_fpga_v9.1.0.exe and downloading the factory recovery files which I installed with ./restore.sh Once that was done I was able to install the userfile_hw.flash according to the user guide. Interestingly, in this version of the instructions, the --offset=0x0 but when programming (as you explained) the --base=0x0800_0000. Cheers, S.
--- Quote Start --- Thanks Dave. I also found the proper installation for my dev. board by going to all the way back to: ftp://ftp.altera.com/outgoing/devkit/91/stratixive_4se530es_fpga_v9.1.0.exe --- Quote End --- You have a kit with an E-series device? So you don't have a GX kit then (which has transceivers)? --- Quote Start --- and downloading the factory recovery files which I installed with ./restore.sh Once that was done I was able to install the userfile_hw.flash according to the user guide. --- Quote End --- Excellent! --- Quote Start --- Interestingly, in this version of the instructions, the --offset=0x0 but when programming (as you explained) the --base=0x0800_0000. --- Quote End --- The readme.txt file in the couple of kits I looked at indicated that the User Manual instructions had some errata. Check the readme.txt in your install area, perhaps it has a similar comment. Cheers, Dave
I'm not out of the woods yet...Yes, I was able to restore the factory backup files using the ./restore.sh and it boots up and runs. However, even though I was able to program the CFI with the user_hw.flash it does not bootup (configure the FPGA), i.e. I don't get the green LED to light up. I tried the following:1)offset 0x0, program at base address 0x0800_0000 fails to boot (according to guide) 2)offset 0x200_0000 (the user HW start from memory map table), base address 0x0800_0000 =>fails to start programming 3)offset 0x002_0000 (factory HW start), program at base address 0x0800_0000, fails to boot 4)tried a simple flashing LED design, the same results, fails to boot P.S. I am using the NIOS II EDS method not the Board Update Portal. Has anyone programmed a Stratix IV 530ES CFI and have it bootup? I am looking for any small design that can be programmed into the 530ES user HW space with the instructions to do it, that work. Preferably a design with a NIOS II and some SW. I have not confidence in the user guide instructions anymore. Thanks, S.
--- Quote Start --- Yes, I was able to restore the factory backup files using the ./restore.sh and it boots up and runs. --- Quote End --- Ok, that is a good start. --- Quote Start --- However, even though I was able to program the CFI with the user_hw.flash it does not bootup (configure the FPGA), i.e. I don't get the green LED to light up. --- Quote End --- To isolate whether its your programming image do the following; 1) Confirm you can program your custom hardware design using JTAG. 2) Confirm that the user area works by programming it with the flash image that restore.sh uses, i.e., program that same image to both the factory area and the user area. Then use the selector dial to select factory or user and confirm that both boot up ok. That'll confirm the MAX II passive serial programmer is working correctly. 3) Rebuild the factory image and flash it to the user area. At that point you will either have confirmed that flash programming works, and perhaps you'll figure out what is wrong with your hardware image. Cheers, Dave
1) Yes, I can program my custom HW using JTAG2) Now, this is where it gets interesting, the restore.sh programs 2 factory restore files, previously created, restore_0 and restore_1. The two are different, one is HW the other is SW and a collection of other bits an pieces. You can't just program them anywhere you wish interchangeably. restore_0 has to go at base 0x0800_0000 (offset=0x20000) and restore_1 has to go at 0x0A00_0000. This is because restore_0 has the NIOS II which needs to boot SW from a specific location. I can individually program restore_0 and restore_1 to the expected bases (0x0800_0000 and 0x0A00_0000) correctly but if I try to program the USER HW at any base (0x0800_0000 or 0x0A00_0000) with any offset, it does not configure the FPGA. Could it be that I am missing something in creating the user.sof ? I figured that if I can download it with JTAG and it works then it is good to use for programming into FLASH, no? Thanks, S.
--- Quote Start --- 1) Yes, I can program my custom HW using JTAG --- Quote End --- Great. That eliminates one potential issue :) --- Quote Start --- 2) Now, this is where it gets interesting, the restore.sh programs 2 factory restore files, previously created, restore_0 and restore_1. The two are different, one is HW the other is SW and a collection of other bits an pieces. You can't just program them anywhere you wish interchangeably. restore_0 has to go at base 0x0800_0000 (offset=0x20000) and restore_1 has to go at 0x0A00_0000. This is because restore_0 has the NIOS II which needs to boot SW from a specific location. I can individually program restore_0 and restore_1 to the expected bases (0x0800_0000 and 0x0A00_0000) correctly but if I try to program the USER HW at any base (0x0800_0000 or 0x0A00_0000) with any offset, it does not configure the FPGA. Could it be that I am missing something in creating the user.sof ? I figured that if I can download it with JTAG and it works then it is good to use for programming into FLASH, no? --- Quote End --- It won't be the .sof that's missing something, it'll be in the conversion from .sof to SREC (.flash). Look at the Flash memory map in the user guide (Appendix A): http://www.altera.com/literature/ug/ug_sivgx_fpga_dev_kit.pdf Add 800_0000h to all these addresses to get the flash memory map as viewed by the NIOS II processor (since it maps the flash to this address). Now look at the offsets you are using when creating the .flash files. They should correspond to the offset to the factory hardware image, user hardware image, or software images respectively. The fact that you are using both 800_0000h and A00_0000h implies that your board has the dual-die flash - is that correct? (Mine does). There is a --dual-die option to one of the programs that creates the flash images. I suspect this is required to correctly issue flash programming sequences or sector erase sequences, since the dual-die version has to be treated as two separate flash devices. If these comments don't result in an "Ah-ha!" moment for you, let me know, and I'll go back and look at how to do it on my boards. Cheers, Dave
Sorry but the saga continues. Yes, this looks like a dual-die. I tried it with and without the --dual-die and no help. I tried:sof2flash --input=yourfile_hw.sof --output=yourfile_hw.flash --offset=0xC20000 followed by: nios2-flash-programmer --base=0x08000000 yourfile_hw.flash and I get the message: "the input is too large to fit (device size = 0x2000000)" --- I also tried: sof2flash --input=<yourfile>_hw.sof --output=<yourfile>_hw.flash --offset=0x00C20000 --pfl --optionbit=0x00018000 --programmingmode=PS (with/without --dual-die) and I get the same message. S.
FYI: I can confirm that I get the same "input file is too large error" for Quartus v11.1sp1 and v12.1. Which version are you using?If you try and verify the image in flash, the programmer crashes (Quartus 12.1 generates an Abort under Windows 7). I don't find that particularly encouraging :( I'll continue looking at the Stratix IV GX kit tomorrow, but tonight I'll have a play with a Cyclone IV GX Starter Kit - I'm pretty sure I've used the nios2-flash-programmer successfully with that kit. Cheers, Dave
Because this is an older board (2009) it is has a dual-die CFI so one of the user guides suggests programming at base 0x0A00_0000. Tried programming with:1)offset 0xC20000, I get a message that it is too large to fit, 2)offset 0x0, it programs but does not boot. Tried every permutation of offset and base address. There seems to be a disconnect between the instructions and the CPLD (MAX2). I am running out of options. I don't know what CFI memory map the CPLD is configured with, the user guide has changed several time over the years and so has the memory map and programming commands. The only thing that works is to run ./restore.sh with the factory .flash files. I hope Dave has the answer for me. Thanks, S.
As I commented above, I confirmed that nios2-flash-programmer would fail with the same error message for the 230K board. I systematically went through the sequence of tests in the attached .txt file (it was too large post inline), and wouldn't you know it, it works fine now!I have a second 230K board that I will try this on tomorrow. I wonder if the issue was not in the programmer, but in the NIOS processor. In the systematic tests, I configured the board with an .sof from the v11.1 zip - perhaps that design corrected the error that causes the programmer to fail ... My suggestion to you: 1) Configure your board with the factory_recovery/s4gx530_fpga_bup.sof 2) Then in a NIOS II IDE shell, change to the factory_recovery folder, and issue the command nios2-flash-programmer --base 0x8000000 --debug --dualdie restore_s4gx530_fpga_bup.flash and let me know if that works. Otherwise try the systematic steps in the .txt file and see where you differ. Cheers, Dave
I just re-flashed the image on my second 230K board. Without the --dualdie option I would get the "input file to big" error, but the flash was updated fine using --dualdie.Try the sequence above and it should work for you. If it does not, program the MAX II with its factory recovery image, then the FPGA with the BUP .sof, and then try again. Chat with you in two weeks. Cheers, Dave
I just came across this "list of known issues" with the Stratix IV kit:http://www.altera.com/support/kdb/solutions/rd06242009_293.html I suspect the "BUP loading user software image" section describes the issue you were seeing. Cheers, Dave