I have implemented a PCIe 2.x 128-bit Avalon-ST endpoint on the Stratix IV Development Kit.I have so far been able to read the configuration space of the device; however, I have been unable to observe, via signal-tap, a write operation on the FIFO. The FIFO is Avalon-ST (and packet) enabled. The *in_ready and *out-ready of the FIFO are both asserted, of which, means that the FIFO is ready to receive data from the PCIe core and its 128-bit Avalon-ST interface. I am asking if someone can look over my IO connections for this particular development kit to make sure that I have all of the required clocks, controls, etc. setup so that the SERDES interface functions properly. I believe I do have it connected properly; however, I just need to bounce it off someone else. The documentation with-regards-to custom endpoint development, outside of the QSsys flow, is very limited; therefore, I may have missed a vital IO connection? If not, it must have something to do with my RTOS interface to the PCIe device. I have used this same RTOS access method on a 64-bit Avalon-MM endpoint implementation without issue. Any feedback would be greatly appreciated! Thanks!
Check out the document and designs posted with this thread:http://www.alteraforum.com/forum/showthread.php?t=35678 The thread discusses the Qsys PCIe core, which you are not using, but it has a top-level file for the Stratix IV GX Development kit, which is what you are after (for comparison with your values). Cheers, Dave