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Altera_Forum
Honored Contributor I
1,086 Views

Stratix IV GX Development Kit - QDRII UniPHY Pinning

I'm using the Stratix IV GX Development Kit to evaluate QDRII(+)-SRAM. 

I've configured the QDRII+-MegaCore for that Stratix IV FPGA without any problems.  

 

The generated code was synthesized by Quartus 11.1sp2. 

But the fitter throws the following error: 

 

Error (176172): Can't place node "qdr2top1_k_n" -- node is a differential I/O node 

 

I can't understand the problem, because: 

 

- I'm using the provided golden_top design (hdl + all assignments) 

- The referred "qdr2top1_k_n" node IS a differential I/O node and is placed properly together with "qdr2top1_k_p" at a Strobe/nStrobe pin pair. 

 

Any suggestions?
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9 Replies
Altera_Forum
Honored Contributor I
48 Views

 

--- Quote Start ---  

 

Any suggestions? 

--- Quote End ---  

I haven't tested the QDRII+, however, I do have the following two options in my Tcl pin assignments script. 

 

# Clock if {0} { set pin(qdr_top0_k) {PIN = P23, IOSTD = "DIFFERENTIAL 1.5-V HSTL CLASS I", SLEW = 3, TERMOUT = "SERIES 50 OHM WITH CALIBRATION"} set pin(qdr_top0_k(n)) {PIN = N23} } else { set pin(qdr_top0_k) {PIN = P23, IOSTD = "1.5-V HSTL CLASS I", SLEW = 3, TERMOUT = "SERIES 50 OHM WITH CALIBRATION"} set pin(qdr_top0_kN) {PIN = N23, IOSTD = "1.5-V HSTL CLASS I", SLEW = 3, TERMOUT = "SERIES 50 OHM WITH CALIBRATION"} } Try the second option. 

 

The PIN, IOSTD, SLEW, and TERMOUT settings get translated to 

 

IOSTD {set_instance_assignment -name IO_STANDARD $val -to $port} PIN {set_location_assignment -to $port "Pin_$val"} SLEW {set_instance_assignment -name SLEW_RATE $val -to $port} TERMOUT {set_instance_assignment -name OUTPUT_TERMINATION $val -to $port} later on in the Tcl script. You can just use the set_instance_assignment versions directly. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
48 Views

Thank you Dave for your helpfull answer. Differential pins should be set to a differential IOSTD. I got that parallel to your post. The ALTERA golden-top assignments miss on that. 

 

Is your pin assignment skript made by yourself or is it some ALTERA-provided skript?
Altera_Forum
Honored Contributor I
48 Views

I've found my IP-Core related Tcl pin assignments script. 

But unfortunately it conflicts with the assignments set by the golden_top design which was originally delivered with an altmemphy-based QDRII+ IP-Core. 

 

For now I'm a bit lost which of the conflicting assignments to change. 

 

I will try next to keep the location assignments of the golden_top design and remove *all* other IO-Assignments from the golden_top, so that they can be set by the QDRII-Uniphy-Core.
Altera_Forum
Honored Contributor I
48 Views

I've just created a service request regarding this.

Altera_Forum
Honored Contributor I
48 Views

I want to share the solution from ALTERA mySupport: 

 

There is a working QDRII SRAM IF design here (http://www.alterawiki.com/wiki/design_example_-_stratix_iv_qdr_ii_sram_uniphy_400mhz_x18). 

 

Quartus will synthesize and fit it without any complains out of the box. 

To have Quartus generate a simulation model from the provided skripts you'll have to adapt the hardcoded paths in the mentionend skripts to your local environment. 

Modelsim DE simulates the respective output out of the box. 

 

+1 for ALTERA mySupport
Altera_Forum
Honored Contributor I
48 Views

 

--- Quote Start ---  

 

There is a working QDRII SRAM IF design here (http://www.alterawiki.com/wiki/design_example_-_stratix_iv_qdr_ii_sram_uniphy_400mhz_x18). 

 

Quartus will synthesize and fit it without any complains out of the box. 

 

--- Quote End ---  

 

 

Great! Thanks for sharing the SR response. 

 

Did you try this under Quartus 11.x or 12.0? 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
48 Views

I've used QuartusII 11.1sp2. I will try it with QII 12 until the end of this week. 

 

I forgot to mention, that it works with 400MHz without any flaws in StratixIV GX Development Kit HW! 

 

Now ALTERA has set an working environment (SW + HW) in an unknown field for me, I can focus on my 

actual assignment (QDRII(+)-SRAM IF Controller Concept / Evaluation). 

 

I forgot to mention also: 

 

+1 for Altera|Forum :)
Altera_Forum
Honored Contributor I
48 Views

 

--- Quote Start ---  

Great! Thanks for sharing the SR response. 

 

Did you try this under Quartus 11.x or 12.0? 

 

Cheers, 

Dave 

--- Quote End ---  

 

 

It works under QII 12.0 as well.
Altera_Forum
Honored Contributor I
48 Views

 

--- Quote Start ---  

It works under QII 12.0 as well. 

--- Quote End ---  

 

 

Thanks! 

 

I've been meaning to test the QDR II+ on the Stratix IV kit. Its good to know there is a working example available. 

 

Cheers, 

Dave
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