Stratix IV GX Pin Assignment

[Altera_Forum]

Hi, 

 I'm working on the Stratix IV GX 230 board and I'm trying to use the Triple Speed Ethernet in RGMII mode with MDIO. I did everything well untill the moment I needed the PIN in order to connect the MAC with the PHY. But I couldn't find any information concerning the following pin: For the MDIO: -mdio_oen -mdio_in -mdio_out -mdc  For the RGMII: -tx_control_to_the_triple_speed_ethernet_0 -rx_controle_from_the_triple_speed_ethernet_0 -tx_clk_from_the_triple_speed_ethernet_0 -rx_clk_from_the_triple_speed_ethernet_0 -rgmii_in_from_the_triple_speed_ethernet_0 -rgmii_out_to_the_triple_speed_ethernet_0  All I could find was the PHY PIN assignment for the SGMII with LVDS transceiver there: http://www.altera.com/literature/manual/rm_sivgx_fpga_dev_board.pdf  And even the documentation about the bank of IO couldn't tell more about that.  Have anyone ever managed to use the RGMII with the Stratix IV in order to have an Ethernet output?  Thank you.  Michel

[Altera_Forum]

From what I see you can only use the Marvel PHY on this board in SGMII mode and not RGMII. 

As for the MDIO pins, connect mdc to ENET_MDC and make a small tristate output for ENET_MDIO: when mdio_oen is 0 it should be an output with the value mdio_out, and when mdio_oen is 1 it should be an input, and the value fed to mdio_in.

[Altera_Forum]

Thank you for your answer Daixiwen. 

As you said I used the SGMII mode for the TSE and I connected the PIN as indicated in the User Guide. I also connected MDC and MDIO (tristate) with the PIN that were indicated by the same User Guide. Then I ran the Simple Socket Server in both RGMII and normal mode (the samples that are given in Eclipse Nios 2) with the DHCP unused but it seems that there is still no PHY detected in the design. And whenever I try to use telnet to the board with telnet I get no answer.  This is strange because even if there is no PHY, the SSS says that it's listening on port 30 with an Error: No PHY detected.  I've seen that other people had this problem before but I still don't see any answer to my problem.  Has anyone find the solution to this problem?  Thank you in advance.

[Altera_Forum]

No PHY detected seem to indicate that the MDIO interface isn't working. How did you make the tristate buffer for the MDIO data signal? 

Put some Signaltap probes on MDC, the 3 MDIO signals from the TSE, and the tristated MDIO pin to check that it is working properly and that you get an answer from the PHY.

[Altera_Forum]

I'm making my tristate MDIO data signal like that : 

 -- the_tse_0  ref_clk_to_the_triple_speed_ethernet_0 => system_clk,  rx_recovclkout_from_the_triple_speed_ethernet_0 => rx_recovclkout,   rxp_to_the_triple_speed_ethernet_0 => rxp,  txp_from_the_triple_speed_ethernet_0 => txp,  mdc_from_the_triple_speed_ethernet_0 => mdc,  mdio_in_to_the_triple_speed_ethernet_0 => mdio_inout,  mdio_oen_from_the_triple_speed_ethernet_0 => system_mdio_oen,  mdio_out_from_the_triple_speed_ethernet_0 => system_mdio_out  );    mdio_inout <= system_mdio_out when (system_mdio_oen = '0')  else 'Z' when (rising_edge(clk));  And I've put some probes on the signal you said but everytime that I try to read these signal, I get : -a clk signal on mdc and mdc_out_from_the_triple_speed_ethernet -'1' in mdio_inout mdio_in mdio_oen and mdio_out signal.  My trigger condition is a falling edge of mdio_oen. According to my equation, this is right but is it normal to see mdio_in and mdio_oen mdio_out '1' at the same time?

[Altera_Forum]

Does mdio_oen always stay at 1? That's strange, it should go to 0 when the TSE wants to read the PHY's answer. You should also se some toggling on mdio_out and the mdio pin. 

 I'm not sure how Quartus will understand and synthesize this: mdio_inout <= system_mdio_out when (system_mdio_oen = '0') else 'Z' when (rising_edge(clk));but it probably won't be what you expect. Just ule a regular buffer: mdio_inout <= system_mdio_out when (system_mdio_oen = '0') else 'Z';No need to take the clock into account here.

[Altera_Forum]

Thanks for your help Daixiwen, I have already changed the buffer to what you said (because it had a strange behavior before) and my mdio_oen goes 0 when he wants the PHY's answer and 1 otherwise. 

I can also see some toggling on the mdio_out pin which I believe is reassuring..  I'm compiling the project and I'll see if my PHY will finally work after that.

[Altera_Forum]

Well I have done all of this my MDIO_inout is correctly following my MDIO_out and my MDIO_in is following my MDIO_inout with a MDC frequency of 2MHz. 

 And still, it seems that my PHY isn't detected by my iniche_init.c process. I still have the: prepped 1 interface, initializing... [tse_mac_init]  Then nothing.  My design is composed of the Nios II connected to a TSE via two SGDMA and an on_chip_mem. The TSE is configured with SGMII, MDIO, SGMII Bridge enabled, and I have connected the TSE output pin to: mdc -> PIN_AH34 mdio_inout -> PIN_M33 txp -> PIN_L29 rxp -> PIN_AC31   I'm quite sure that the tri state bus is working fine with the signaltap. And the software I'm loading into the Nios II is a Simple Socket Server configured without the DHCP.  I have already tried to use the TSE in GMII, RGMII mode.   Does anyone knows what I could try to do in order to make this Triple Speed Ethernet output work?  Thank you by advance.  Michel

[Altera_Forum]

Do you see the PHY's answer on the MDIO pin? i.e. is there any time with the mdio pin or mdio_in different than 1 when mdio_oen is 1?

[Altera_Forum]

I have no answer coming from the PHY when the MIDO_oen = '1'. 

The signal mdio_out mdio_in and mdio are changing only when the mdio_oen = '0'.  Does that mean that my transceiver isn't working well? I use a LVDS transceiver configured by the Triple Speed Internet. I haven't changed the default setting for this component.

[Altera_Forum]

It's strange because I just found a documentation which says that it's actually possible to instanciate RGMII with the Stratix IV GX. 

http://www.altera.com/literature/manual/rm_siv_gx_si_devkit_board.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=stratix%20iv%20gx%20mdio  Still it says that the PIN for the RXP is D31 instead of this document: http://apegate.roma1.infn.it/~ammendola/altera/s4gx_pcie_b.pdf In which we can see that the RXP pin is the AC31.  Which of these document should I use in order to link my rxp, txp, mdio, mdc finally?

[Altera_Forum]

Sure the FPGA is able to use the RGMII interface with the PHY, and so is the PHY, but from the schematic (page 13) you can see that the PHY's RGMII interface isn't connected, so you are stuck with SGMII on that board. 

You should first ensure you have a correct MDIO communication with the PHY. The MDIO isn't used to transfer packets, but just to configure the PHY and get statistics. Once you have this, you know that the PHY is running. When checking the PHY's answer on the MDIO but, you must keep in mind that the TSE driver will try all the 32 possible PHY addresses, and will only get an answer on one of theme. Therefore you must either have a very big signaltap memory buffer to be sure to capture all the transactions, or trigger on something more special (such as mdio_oen at 1 and mdio_in at 0 at the some time, which would indicate a PHY communication). Once you can communicate with the PHY, you can focus on the SGMII interface again.  When you have conflicting information about the pins between the user manual and the schematic, always trust the schematic. Bogus kit documentation is a recurring problem with Altera.

[Altera_Forum]

Thank you Daixiwen for your help, 

Now that I put my signaltap to trigger on the mdio_oen = '1' and mdio_in = '0' I do have an answer coming from the PHY which is a small acknoledgement bit in the mdio_in.  I guess my PHY is communicating with my TSE but what do you mean by focus on the SGMII again? I haven't done anything for the SGMII since I thought all the data coming out from the TSE were going to the PHY with the TX_p pin.  I finally trusted the schematics and put the PIN_AC31 instead (anyway I had errors with the D31).

[Altera_Forum]

It's a good sign that you get an answer from the PHY. Does the software say it detected a PHY? Is it set in gigabit mode? 

As for the SGMII interface you are right, the data goes to the PHY through the TX_p/TX_n pair and that's all that should matter.

[Altera_Forum]

The software doesn't say anything about detecting the PHY. 

I haven't set it in Gigabit mode since I thought it was already set automatically by the TSE itself. Could you please tell me how to set the TSE in Gigabit mode please?

[Altera_Forum]

So this means there is still a communication problem on the MDIO line... could you put a screenshot of the MDIO communication, when the PHY responds? 

For the gigabit mode I was talking about the PHY. Check if there is a led on the board that tells if the PHY is in gigabit mode.

[Altera_Forum]

Thank you Daixiwen, I have put a screenshot of my Signaltap in the following PDF (sorry I couldn't upload anything else because of the firewall) 

 Everytime I have my Simple_socket_server working I have the following messages:   InterNiche Portable TCP/IP, v3.1   Copyright 1996-2008 by InterNiche Technologies. All rights reserved.  prep_tse_mac 0  Can't read the MAC address from your board. We will assign you a MAC address.  Please enter your 9-digit serial number. This is printed on a  label under your Nios dev. board. The first 3 digits of the  label are ASJ and the serial number follows this.  -->Created "Inet main" task (Prio: 2) Created "clock tick" task (Prio: 3)  123456789 123456789 Your Ethernet MAC address is 00:07:ed:ff:cd:15 Static IP Address is 0.0.0.0 prepped 1 interface, initializing... [tse_mac_init]   And since I'm using the PCIe port of my board (which is plugged on my motherboard) I can't really see LED blinking for the Gigabit Mode. But I'm quite sure that none of these LED are blinking.  I also tried to disable the DHCP mode in my software but it comes to the same thing in the end.  Again thank you for helping me.

[Altera_Forum]

Could you sample more bits, so that we can see the full message? You can use a slower clock to sample the bus, the MDIO clock is supposed to be <= 2.5MHz 

I find it strange that the driver doesn't prinf anything about the PHY. And where does the 123456789 come from? Could you run the PHY exploring routine in a debugger, to see what it does?

[Altera_Forum]

The screenshot I made was a zoom of the sample, the MDIO clock for the signaltap is a 100MHz clock. But my TSE clock is a 150MHz clock and the MDIO host clock division is 60 for an MDIO clock of 2.5MHz. 

 I also find it strange that the driver doesn't printf anything about the PHY but I haven't changed anything about the software. The 123456789 comes from me since it's asking me to type my serial number, I've read the source code and it only generate a MAC ADDR according to this serial number, I don't think it really matters in this case.  What do you mean by the PHY exploring routine? Do you want me to run the Simple_socket_server software in debug mode?

[Altera_Forum]

Well I did everything once again and this is what I get from the simple_socket_server_RGMII with the following options: 

-DHCP disabled -TCP enabled  The PIN used for the mdc and mdio_inout are the same than those used in the Altera niosii-triple-speed-ethernet-4sgx230-v10-1/tserd_4sgx230 design which are: enet_tx_p PIN_L29 enet_rx_p PIN_AC31 enet_mdc PIN_AH34 enet_mdio PIN_M33  I also changed the get_mac_addr() function to:  int get_mac_addr(NET net, unsigned char mac_addr[6]) { error_t error = 0;  mac_addr[0]=0xB7; mac_addr[1]=0xA7; mac_addr[2]=0xED; mac_addr[3]=0xFF; mac_addr[4]=0xFF; mac_addr[5]=0xFF;  printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x\n", mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]); return error; }   And when I run my software the message I got is: ************************************************************* InterNiche Portable TCP/IP, v3.1   Copyright 1996-2008 by InterNiche Technologies. All rights reserved.  prep_tse_mac 0 Your Ethernet MAC address is b7:a7:ed:ff:ff:ff Static IP Address is 192.168.1.234 prepped 1 interface, initializing... [tse_mac_init] INFO : TSE MAC 0 found at address 0x00000400 ERROR : MAC Group[0] - No PHY connected! INFO : PCS[0.0] - Configuring PCS operating mode INFO : PCS[0.0] - PCS SGMII mode enabled ERROR : PHY[0.0] - No PHY connected! Speed = 100, Duplex = Full OK, x=0, CMD_CONFIG=0x00000000  MAC post-initialization: CMD_CONFIG=0x04000203 [tse_sgdma_read_init] RX descriptor chain desc (1 depth) created mctest init called IP address of et1 : 192.168.1.234 Created "Inet main" task (Prio: 2) Created "clock tick" task (Prio: 3)  Simple Socket Server starting up [sss_task] Simple Socket Server listening on port 30 Created "simple socket server" task (Prio: 4) ***************************************************************** I also attached the signaltap screenshot.  It seems that my PHY still doesn't work even if my MDIO get an answer coming from the PHY.  Thank you

[Altera_Forum]

This message hereERROR : PHY - No PHY connected! Speed = 100, Duplex = FullSays that without communication with the PHY, the driver automatically switched to 100Mbps mode. If the PHY has negotiated a link at 1Gbps, it won't work. Even if you forced the driver into gigabit mode I'm not sure it would work, as the PHY requires some initialization. 

The function that does the PHY detection is called alt_tse_mac_get_phy). It could be a good idea to run it step by step and see if it detects anything on the mdio bus.  Looking back at your screenshot, I'm not sure what we are seeing is in fact an answer from the PHY. It could just be because of the delay before the pull-up brings the line back to a '1' level. If you look closer at tho code, you'll see that the driver tries all 32 PHY addresses, looking for an answer. One of them should show a different result on the MDIO line. Now I may sound stupid but you never know... Are you sure the ENET_RESETn signal isn't kept low by the FPGA?