Hi,
my instantiated altera pll goes out of lock periodically when I use the 50MHz clock svb_clk_50 (FPGA 2).
When I use the 100 MHz clock input svb_clk_p as pll clock reference everything is working fine.
My clock constraints for this project are:
create_clock -name {svb_clk} -period "100 MHz" [get_ports {svb_clk_p}]
create_clock -name {svb_clk_125} -period "125 MHz" [get_ports {svb_clk_125_p}]
create_clock -name {svb_clk_50} -period "50 MHz" [get_ports {svb_clk_50}]
Also the schematic for the board shows a pull-up/pull-down connected to clock svb_clk_50, whereas the FPGA 1 clock sva_clk_50 has no pull-up/pull-down.
Is there a known problem with this clock?
Jan
