FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
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Stratix V Dev Board - Presetting Clocks

Honored Contributor II

Hi All... First thanks in advance for the help. We have been working with the dev board for a while but have not had a need to change flash until now. To make remote testing easier we need to put in a user load which is working nicely but we also need to have some clocks preset as well. Upto now we were using Clock Control but saw a post that said you could preload such that CPLD would auto set it. Question is how?? If its in a doc can you please point me to it? Thanks.

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