FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5234 Discussions

Stratix V Dev Board - Presetting Clocks

Honored Contributor II

Hi All... First thanks in advance for the help. We have been working with the dev board for a while but have not had a need to change flash until now. To make remote testing easier we need to put in a user load which is working nicely but we also need to have some clocks preset as well. Upto now we were using Clock Control but saw a post that said you could preload such that CPLD would auto set it. Question is how?? If its in a doc can you please point me to it? Thanks.

0 Kudos
0 Replies