Stratix V Dev Board - Presetting Clocks

FPGA, SoC, And CPLD Boards And Kits

FPGA Evaluation and Development Kits

Stratix V Dev Board - Presetting Clocks

774 Views

Hi All... First thanks in advance for the help. We have been working with the dev board for a while but have not had a need to change flash until now. To make remote testing easier we need to put in a user load which is working nicely but we also need to have some clocks preset as well. Upto now we were using Clock Control but saw a post that said you could preload such that CPLD would auto set it. Question is how?? If its in a doc can you please point me to it? Thanks.

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.