Stratix V Development Kit Transceiver Clock Settings

FPGA, SoC, And CPLD Boards And Kits

FPGA Evaluation and Development Kits

Stratix V Development Kit Transceiver Clock Settings

1,152 Views

I'm new to FPGA and need to use the transceiver toolkit to transfer the data at rate from 5000MBps up to 10000MBps. After searching some information I download one sample project from http://www.alterawiki.com/wiki/transceiver_toolkit, which is as follows:

http://www.alterawiki.com/uploads/7/75/sv_7ch_11p3gbps.qar

http://www.alteraforum.com/forum/attachment.php?attachmentid=11723&stc=1

For this project, the Data rate by default is set as 11300MBps. While when I was trying changing it to some random value between 5000MBps and 10000MBps by using Qsys, some of the value cannnot be set. Even though some of the value is set successfully and can compile without any problem. But the thing is after I program it into the FPGA, the transceiver links cannot operate properly.

Can I know what is the rule to adjust the base rate for this board?

21 KB

Link Copied

0 Replies

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.