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Stratix V GS DSP Development Kit - XCVR Reference Clock SMA's

Honored Contributor II

I am developing a project using the Stratix V GS DSP development kit. I need to deliver a clock to the high speed transceivers on the HSMC ports, however due to the design of the dev kit, all but one of the dedicated reference clock pins are not accessible to external reference clocks (don't know why it was designed that way!). In my current design I have been using one of the dedicated PLL clock inputs to drive an FPLL by the transceivers, the output of which can in turn drive the CMU PLLs in the transceiver bank. The trouble with this approach is there is theoretically quite a lot of jitter as a result - an LVDS input, the global clock network, two PLLs, and then the transceiver clock networks. 


On the board there are a pair of SMA connectors (CLKIN) which upon examining the schematic feed through a low jitter clock multiplexer and in to the dedicated reference clocks of the transceiver bank. However I am struggling to understand the termination scheme used. Attached is an image from the schematic. 




Each SMA (which I presume is 50 Ohm?) is terminated with a 100 Ohm resistor to ground (as opposed to differential between the SMAs!). Then both are AC coupled using 100nF capacitors and then terminated again using a 124 Ohm resistor to GND and an 84.5 Ohm resistor to 3.3V. 


By my calculation, the bias termination after the AC coupling (124 || 84.5) equates to an effective 50 Ohm termination which on its own would make sense. However if we add in the effect of the DC coupled 100 Ohm termination, that equates to an overall input impedance of 33 Ohm!  


I don't understand why a pair of 50 Ohm SMA connectors which are supposedly differentially routed would have not only a single-ended termination each rather than differential, but also why this termination would be effectively 33 Ohm which will cause a massive impedance mismatch. 


Is there something I'm missing?
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3 Replies
Honored Contributor II



Do some reading about LVPECL. For example, see Figure 3 in this document: 




Look familiar? 


Honored Contributor II



The capacitor and (124 || 84.5) termination make sense from an impedance point of view - and match what is in that document, so that now makes sense as a differential termination.  


However there are additional 100Ohm terminations to ground which if figure 3 from that document is anything to go by should be at the source, not a termination. The termination resistance as a result ends up being 33Ohm which is not correct. 


Honored Contributor II

Tom - 


I've never used one of those SMA clock inputs but that exact circuit is used on many Altera dev kits, so one would ASSUME that it is "correct" and works as intended. But honestly I'm not sure what type of equipment would generate a differential clock compatible with that circuit. The manuals for your dev kit don't give any guidance on that. I'm guessing you could feed just about any diff clock in there and it would work, such as LVDS. The termination would not be perfect, but it would probably work. 


Too bad Altera doesn't man this forum with more (any?) employees who could answer questions like this without requiring a service request. SRs typically take time and the results are not available publicly (to help other users) unless Altera decides to post them in the knowledge base. The Xilinx user forum, by comparison, is manned heavily by Xilinx employees and they respond promptly with good answers. Very beneficial for the user community. I wish Altera would discover the benefits of that approach. 


I trash Altera pretty frequently on this forum for their deficiencies vs. Xilinx, but I do not see things getting any better. In fact they may be getting worse. Not surprising with Intel now making the calls. My personal opinion is that the slide within Altera started several years ago as they were getting their butt kicked by Xilinx, and more than anything else that's what led to the sellout. Easier to sell than to fix the problems. In the end I think this takeover is going to be a very bad thing for competition in the FPGA space. Time will tell.