Stratix V GT LL PHY TTK

[iiwan]

I need to test Stratix V GT transceiver channels at speed 27 Gbps. At that speed I can only use Low Latency PHY IP core. It has own avalon slave and reconfig xcvr bus. I tried to use both to connect to JTAG to Avalon master bridge but did not get any results. And did not find any example design for my use case. For Arria 10 I found a lot of designs, but there are everything in IP core, all things as ADME and PRBS. Any help please.

[CheePin_C_Intel]

Hi,

As I understand it, you have some inquiries related to the SVGT XVCR. To ensure we are on the same page, just would like to check with you on the following:

1. Mind further elaborate on your problem observation when you mention "did not get any results". Some screenshots will be helpful.

2. Are you trying to use transceiver toolkit to connect to the transceiver? 

3. Are you trying to write to certain register of the PHY, and there is no response at all? 

4. How do you connect the JTAG master to the low latency PHY? Are you using Qsys?

5. Are you using any example design from Intel or if you are creating your design from scratch in RTL?

Please let me know if there is any concern. Thank you.

[CheePin_C_Intel]

Hi,

As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.