Stratix V Kit-Programming SiLabs 5338 w/ FPGA

[Altera_Forum]

I have the Stratix V GX development kit, that has two SiLabs 5338 devices that can be programmed using the Clock Control GUI and the JTAG programmer.  

 What I want to be able to do is program the Si5338s using the Stratix V FPGA on the board through the MAX V CPLD.   The CPLD Verilog code is included as part of the kit. However, it does NOT included any documentation like a memory map or programming instructions that I can find.   Has anybody done this? What would eventually happen is that we would use a NIOS core inside the FPGA to program the clocks after the FPGA boots.  If anybody could point me to any kind of documentation, that would be great.  Thank You.

[Altera_Forum]

Is the FPGA also connected to the I2C interface to the chips? If it is, then you could create an I2C master in the FPGA. 

 If not, how is the MAX V connected to the Stratix V?  (Sorry, I don't have this kit installed - post the schematic if you want me to look at it)  File an Altera service request asking for details about the MAX V memory map from the perspective of the Stratix V.  If you're impatient, then create a Modelsim simulation and reverse-engineer the memory map. Since you have the code to the MAX V, you should be able to figure out most things by reading the code, and then create a transaction in the simulation that exercises what you "think" is correct to confirm it.  The JTAG interfaces typically use the SLD Virtual JTAG core, and since you can read the MAX V code, you can tell most of what you need to for accessing the MAX V via that route. However, for your application, you need access from the Stratix V side.  Cheers, Dave

[Altera_Forum]

Dave, 

 The I2C is not connected to the FPGA. Only through the CPLD.  A google search for MNL-01063-1.3 will result in the rm_svgx_fpga_dev_board.pdf Reference Manual.  Page 15 has the connections. Yes, the JTAG is a Virtual JTAG core.   The FPGA and CPLD are connected using the FSM bus where the FPGA drives a Chip Select into the CPLD.   A service request has been filed... but you how long that can take sometimes. You are correct, if I HAVE to, I can reverse engineer the whole programming sequence...   Thanks Paul

[Altera_Forum]

--- Quote Start ---   The I2C is not connected to the FPGA. Only through the CPLD.  A google search for MNL-01063-1.3 will result in the rm_svgx_fpga_dev_board.pdf Reference Manual.  Page 15 has the connections. Yes, the JTAG is a Virtual JTAG core.   The FPGA and CPLD are connected using the FSM bus where the FPGA drives a Chip Select into the CPLD.    --- Quote End ---   Ok, this is pretty much duplicating what is done on a lot of their other boards.    --- Quote Start ---   A service request has been filed... but you how long that can take sometimes. You are correct, if I HAVE to, I can reverse engineer the whole programming sequence...    --- Quote End ---   Given that they're using a parallel bus with separate address and data, you've got a head-start in that you do not need to decode a multiplexing address/data bus. All you need to figure out is the address map of the MAX V.   Have you looked that the code? Perhaps you'll get lucky and the code was written by a "nice" engineer who wrote the address map in the comments ...  In my experience that is asking a little too much from the code delivered with these kits, but like I said, you might get lucky ... :)  Cheers, Dave