Stratix10 Etile reference clock level questions - Intel Community

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Stratix10 Etile reference clock level questions

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Is the clock level of e-tile only lvpecl?Is LVDS ok?

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269 Views

HI,

It's not recommended to use LVDS.

Pls stick with LVPECL for proper operation as highlighted in Stratix 10 datasheet.

Thanks.

Regards,

dlim

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269 Views

hi,

I hope I have clarified your doubt.

For now, I am setting this case to closure.

Thanks.

Regards,

dlim

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