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Stratix2/Nios2 dev board, problem with SSRAM

Honored Contributor II


I'm a newcomer to design with Altera FPGAs. Some weeks ago I was involved in design with an Altera stratix II development board. I'm not 100% sure which board it is, but taking a look at the devices in it I'm pretty convinced is a rohs board. 

I've been following the 1 day tutorial as well as others in order to implement a basic embedded NiosII procesor but didn't succeed to add the external SSRAM. While implementing something more basic with only on-chip memory works at least for the Nios2/Eclipse counter program template, it doesn't when adding the SSRAM. The leds blink somehow randomly. 


I had set the PLL clocks both for the processor and the SSRAM to 85MHz and the delay of the SSRAM clock to 3.38 ns as explained in the tutorial. But I have the impresion that there must be some kind of timing issues, despite TimeQuest doesn't show anyone. Could anybody give a hint on how to debug this. Having a sample project for the Nios2 processor in this kind of board with all the peripherals included would be extraordinary. 


I'm using Quartus 10.0 in W7. 


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