Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
750 Views

Stratix3 Dev Kit, Using HSMC ports as I/O

Hi, Guys, 

 

I've been experiencing I/O problems of the port for about a month but still have no clue of solving it. 

 

First, I got a DVI RX/TX d-card, manufactured by Terasic (http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=68&no=359). I hooked up the card and download the loopback demo made by Terasic. With SignalTapII, I found the pixel clock signal can be recognized by the FPGA chip but can not be used to trigger any internal register of the chip. 

 

Then, I powered on a VGA decoder/digitizer and connect the pixel clock to each of the 40 pins on a HSMC Debug Breakout Header d-card, which is an accessory card in the kit. The result is interesting: 

For some pins, I can observe the input clock waveform in SignalTapII and can use the clock to trigger internal registers of the device; 

For some other pins, the clock waveform is observable but can not bu use as triggering clock of device register; 

For the rest of the pins, clock waveform is not even observable, I got constant 0 or 1 in the SignalTapII. 

 

I'll attach my result along with schematic of both of the d-card I mentioned. 

 

So...does any one know the reason of this problem or any suggestion of work around? 

 

Any help is appreciated, thanks! 

 

Best, 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=1959  

https://www.alteraforum.com/forum/attachment.php?attachmentid=1960  

https://www.alteraforum.com/forum/attachment.php?attachmentid=1961
0 Kudos
1 Reply
Altera_Forum
Honored Contributor I
58 Views

I can't believe it. According to my knowledge, all Stratix 3 pins dedicated as differential I/O can be used single ended. 

- they can feed the FPGA logic 

- they can be acquired by SignalTap, if configured correctly 

 

Is the loopback test expected to work with the DVI card? 

Did you assign suitable I/O standards to then pins?
Reply