StratixIII Dev Kit - Serial RS 232 Substitute?

[Altera_Forum]

I am working on porting a soft-core processor (JOP) on the StratixIII FPGA. The processor ‘listens’ for the program on the serial port. As this board does not have a serial port, is there an alternative of possibly using the FTDI - FT245BL chip and creating virtual serial port on the PC? If so, where can I find information on how this can be done?  

 I’ve tired looking for resources on how to use/interface with this chip or any design examples but have been unsuccessful. Where can I find information on how to use/interface with this chip?   Please point me in the correct direction to working around the serial port problem.   Thanks   Stratix III Development Kit http://www.altera.com/products/devkits/altera/kit-siii-host.html (http://www.altera.com/products/devkits/altera/kit-siii-host.html)

[Altera_Forum]

--- Quote Start ---  I am working on porting a soft-core processor (JOP) on the StratixIII FPGA. The processor ‘listens’ for the program on the serial port. As this board does not have a serial port, is there an alternative of possibly using the FTDI - FT245BL chip and creating virtual serial port on the PC? If so, where can I find information on how this can be done?     --- Quote End ---  The Virtual Com Port (VCP) drivers supplied by FTDI give you serial port access under Windows. Just plug in the FT245BL to a PC USB port and it'll be recognized. Under Linux ftdi_sio gives you the same functionality. In either case, there is no work needed on the host OS side.    --- Quote Start ---   I’ve tired looking for resources on how to use/interface with this chip or any design examples but have been unsuccessful. Where can I find information on how to use/interface with this chip?    --- Quote End ---  The FT245 data sheet has the timing; configure it in 8-bit FIFO mode and implement an Avalon-ST streaming data interface to and from the FPGA. You can then implement logic on top of that. For example, an Avalon-MM master interface.  Take a shot at implementing the logic, and when you have trouble, post your code along with a testbench for simulation in Modelsim, and I'll point out what you need to do.  Actually, I just took a look at the data sheet for the Stratix III kit. It just has HSMC headers, no 100-mil headers. Are you planning on adding an FT245BL to the board? If so, you'll need an HSMC-to-GPIO breakout board (Terasic has them), and a UM245R (that's an FTDI module with an FT245R device on it). If you were thinking of using the FT245 on the kit, you're not going to be able to, as that interface is part of the USB-Blaster logic and its not available for customization.   Cheers, Dave

[Altera_Forum]

Thanks for the quick reply.  

 Yes in fact I was thinking of using the FTDI chip that was on board, but as you pointed out, sadly that's not possible.   What the JOP processor does is that it puts the program from the serial port onto the on-board memory. This question maybe too specific, but is there a way to program the memory (PSRAM in my case) directly through USB. Sorry if this is trival, but I'm new to this, as you might be able to tell.   Thanks for you help once again

[Altera_Forum]

--- Quote Start ---   What the JOP processor does is that it puts the program from the serial port onto the on-board memory. This question maybe too specific, but is there a way to program the memory (PSRAM in my case) directly through USB. Sorry if this is trival, but I'm new to this, as you might be able to tell.    --- Quote End ---  No need to apologize, there's lots of stuff to learn.  When any processor boots, it jumps to a reset vector and executes its first instruction. It sounds like your processor has a small bootloader that will read a program image over a serial port. You have two options;  1) Delete the bootloader code, and just put your code into the memory location of the processor reset vector, or  2) Create a fake serial port that delivers bytes to the bootloader.  Both methods are equally valid.  The second might actually be easier, as you do not have to touch the JOP code. Does it expect a serial port at a specific address? If so, you can map a FIFO to that address, and when the processor reads from that address deliver the next byte of code.  The code could be loaded into an FPGA RAM using a memory initialization file (.mif) as part of the FPGA configuration, or you could load the RAM after power-on, and then enable the processor. The second option would however require you to understand how to hold the processor in reset, and how to create a multi-master bus, where both the processor and JTAG can access RAM.  Is this JOP processor configured as an Avalon-MM master? If so, then multi-mastering the bus is as easy as dropping the processor component into SOPC builder, along with the RAM, and JTAG master.  There's probably lots of things that aren't quite clear to you yet, so keep asking questions.  Have you tried 'booting' this processor in the Modelsim simulator?  Regarding PSRAM; yes, you could program this RAM from USB. You would need an Avalon-MM slave PSRAM controller, and then you can also add this component to an SOPC System.  Cheers, Dave

[Altera_Forum]

Thanks Dave for your all help, 

 I think I'm skipping too many steps and hence not making heads or tails of this problem. So I think I'm going to take it one step at a time.    Where could I find simple design examples for the Stratix III board? There is only one example on the Dev Kit CD, but more would be helpful, espically some that could help me interface with the other components on the board   Thanks

[Altera_Forum]

--- Quote Start ---   I think I'm skipping too many steps and hence not making heads or tails of this problem. So I think I'm going to take it one step at a time.    Where could I find simple design examples for the Stratix III board? There is only one example on the Dev Kit CD, but more would be helpful, espically some that could help me interface with the other components on the board    --- Quote End ---  Here's what I do.  1) Print the schematic (11 inch x 17 inch format)  2) Open any of the projects that ship with the part, and use Create Tcl File for project. Extract all the pin information from that file. Compare the pin list to the schematic and add any missing pins.  Reformat the pin list into something prettier, eg. a Tcl array with a loop that generates Quartus Tcl assignments - check out the de2_basic design at this thread;  http://www.alteraforum.com/forum/showthread.php?t=33462  3) Create a 'basic' top-level design containing the absolute minimal logic, eg., a blinky LED, or just push buttons connected to LEDs (see the de2_basic example).  4) P&R and download, and check things work.  This is your reference design. Check it into a code version system (CVS, Subversion, git, etc.).  5) Create a new design and start to test individual parts on the board.  For example, I make a lot of use of the JTAG interface, either the debug component SLD Virtual JTAG, or more recently the JTAG-to-Avalon-MM master component. This latter component allows you to build an SOPC system with PIO component. You can use that to toggle ports on the FPGA, and then work up from that.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---   .....  5) Create a new design and start to test individual parts on the board. ....   --- Quote End ---         --- Quote Start ---     Regarding PSRAM; yes, you could program this RAM from USB. You would need an Avalon-MM slave PSRAM controller, and then you can also add this component to an SOPC System.   --- Quote End ---     As suggested, I'm testing individual parts of the board. I now want to test the USB on the Stratix III Dev Kit. It seems that data from the USB goes through the FTDI chip or the Cypress chip and through the MAXII and there is a USB data connection between the MaxII and the Stratix III (page 2-8 Stratix III Reference Manual)   I would like to know how I can interface with the USB without using SoPC builder. I simply want to get some data (just some bytes for now) from the computer through USB and store them in PSRAM. How can I do this without using SoPC builder?     Stratix III Development Kit Reference Manual located at: http://www.altera.com/products/devkits/altera/kit-siii-host.html (http://www.altera.com/products/devkits/altera/kit-siii-host.html)

[Altera_Forum]

There is an IP Component called SLD Virtual JTAG. 

 Its not well documented, but it works.  Here's some notes:  http://www.ovro.caltech.edu/~dwh/correlator/pdf/vjtag.pdf  Cheers, Dave