Hello,I screwed up the flash in my StratixIII DevKit, and now I'd like to restore the factory design. According to the User Guide, I have to programm the standard PFL design and than use Quartus to send out the "flash image" of the factory design. However, I discovered that the example designs deployed with the DevKit's documentation are not useful. The devices of these pre-compiled designs do not match: there they are EP3SL150F1152ES, but my board has the EP3SL150F1152C2. The sources (i.e., the example project) of the PFL design is provided by the DevKit's documentation. So, I could compile the PFL design on my own with the appropriate device. When I tried to flash the factory design via PFL, which I had programmed into the FPGA in the ordinary way, no error occurred. But the board is still dead. Obviously, the "flash image" (the .sof file to be written into CFI flash) of the factory design is also an EP3SL150F1152ES, whereas I need a EP3SL150F1152C2. What am I supposed to do? I would like to compile the factory design from scratch, but I don't have the sources. But where can I find it? I'd really be very thankful for suggestions.
Have you any indication, that the ES (prereleased engineering sample) and C2 designs are incompatible? This has been the case previously with a few devices of other FPGA families only.
Yes, I think so.Firstly, when I try to download the PFL FPGA design that has been deployed with the DevKit's documentation, the following error message appears:
Error: Can't configure device. Expected JTAG ID code 0x021020DD for device 1, but found JTAG ID code 0x121020DD.I guess that this stems from the mismatch of devices. Maybe, the built-in USB Blaster in the MAXII device in the engineering sample versions and the mainstream versions of the DevKit is equipped with deviating JTAG IDs in order to point out the difference. Secondly, I perform the whole process of restoring the factory design according to the StratixIII Development Kit User Guide. Everything during configuration works fine, but after a reset or power down / up the MAXII reports "error" by driving the corresponding red/orange ERROR LED on the board. I think, the reason for this originates from the fact, that the factory design .sof-file stratixIII_3sl150_dev_factory.sof has been compiled for the EP3SL150F1152ES .
O.K., you can see from Quartus device selection for Stratix III that the ES devices are actually different. Then the Stratix device has also a different ID. As the shipped board was equipped with the correct design, you can get it at least from Altera support. I didn't check myself, if the design files or the binary as downloadable somewhere from Altera.