StratixV DSP Development Kit with Terasic HSMC Data Converter Cards

Altera_Forum · ‎05-19-2015

I am currently developing a design that uses the DSP Development Kit Stratix V Edition and two of the Terasic AD/DA Data Conversion Cards.

The Data Conversion Cards have two channels each of Analog to Digital conversion that can supposedly run at 150 MSPS.

Has anyone used this board combination and successfully sampled data at the full sample rate of 150 MSPS? If so, what clocking scheme, interface scheme, pin settings, etc did you use?

I can get it to sample as high as 125 MSPS with a relatively clean output but the data looks so bad at 150 (i.e. the data looks like a distorted triangle wave on an O-scope rather than a square wave) that there is no "good time" to capture the data in the FPGA.

What is the maximum data rate that can be achieved over the HSMC interface with these boards?

Can I expect to be able to capture parallel data at 150 MSPS? If so, what am I doing wrong?

Thanks.

Altera_Forum · ‎05-22-2015

Hi there,

Have you tried to loopback directly and see how it goes ?

It's been so long that I couldn't quite remember if we ever push the sample rate to 150 MSPS, but I don't believe the HSMC interface is the bottleneck here.

David from Terasic

Altera_Forum · ‎06-23-2015

Thanks for responding Dav.

What do you mean by "loopback directly"? If you mean have I tried outputting a signal on the DAC and feeding it into the ADC, then yes, I have tried that. If you mean, have I looped the clock back from the ADC, I believe there is a clock out line from the ADC that I am using to register the data in the FPGA.

It really seems like something isn't terminated correctly based on what I am seeing on the O-scope.

Greg

Altera_Forum · ‎07-17-2015

Hi Greg,

Sorry for my late reply.

I was referring to the signals, assuming the reference clock which goes into the ADC/DAC is generated from the PLL directly.

I'll try to take the same daughter card and run it at 150 MHz on our mainboard to see if the waveform is still distorted.

Thanks,

David from Terasic

Altera_Forum · ‎08-12-2015

Any update on this Dav?

Altera_Forum · ‎08-17-2015

Hi Greg,

It seems we need to add timing constraint to the clock source i.e. 50MHz and be in sync. with the data lines strictly.

We will give it a try this week and see how it goes.

Thanks,

David from Terasic

Altera_Forum · ‎09-02-2015

Thanks Dav, any information is greatly appreciated.