I am trying to implement control mode switching in a motion control application. The processor will swap data sets in the memory and use it for some calculation. The FPGA is supposed to swap the data sets and use it for calculation in parallel. This has to be synchronized i.e in a single sample (time frame of 10 microseconds) where both the external processor and the Arria 10 FPGA Soc has to synchronize the switch. Can you give some ideas on how to achieve this?
Processor : PowerPC
FPGA : Arria 10 FPGA SoC
Interface : Serial Rapid IO
Thanks in advance!
The best approach to sync data in this case would be the On chip FIFO with dual clock support.
In this IP, you can set 2 different clocks for data in and data out, with the flexibility of setting the FIFO depth.
Furthermore, if you can export a clock signal from this processor, you can feed it to a PLL, and this PLL will feed the FPGA. Also, you can do it in reverse, if this processor accepts external clock signal, you can use FPGA PLL to feed both FPGA design and external processor.