Hello,I am using the DE2-115 board, with the HSMC-DVI daughter card to get a DVI input into the FPGA. At first I just want to get the video signal going through the FGPA, without any changes but later I plan to store it in the RAM of the DE2-115 to make some VIP on it. So I have my VHDL program, with its system clock and I also have this input video signal which also have a clock....which speed changes with the video resolution. So what should be the best solution to get the input video clock synchronized with my system clock (or the system clock synchronized with the video clock)? I was reading on this forum about reconfiguring the PLL and expanding the input frequency lock range of the PLL (http://www.altera.com/support/kdb/solutions/rd01152007_962.html (http://www.altera.com/support/kdb/solutions/rd01152007_962.html)). Is this the way to have our system clock synchronized with the input video clock? I am a bit confused about this and I would like to avoid working with two clocks. Meach
A dc fifo will do the jb for you irrespective of input clk as long as your system clock is equal to or faster than input data. If faster, the empty flag will be your clk enable inside fpga.