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Altera_Forum
Honored Contributor I
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THDB_ADA HSMC daughter card question

For anyone have experience with the THDB_ADA daughter card, I have 2 questions 

1) Does the card provide extra general purpose I/Os from the FPGA to use? 

2) Do I need an external HSMC connection cable to connect the card with the starter kit? 

 

Thanks for your help 

 

ps: Where did you guys get the board from? Digit key do not have this one in stock
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9 Replies
Altera_Forum
Honored Contributor I
85 Views

Hi, 

I have limited experience of this card having been trying for the last few weeks to implement a digital control circuit for an optical comms application but am currently unable to get it working in single ended operation. 

 

I use it with a Cyclone III starter kit and there is a HSMC connector on it which the ADA board clips into. 

 

The pinout for the HSMC connector info can be downloaded from the Terasic website. The connector for the CIII starter kit is apparently smaller than a standard HSMC connector but there are some unused ports but I have not needed to use any and am not sure where they appear on the board.  

 

You can purchase the board (and starter kit) from Altera website but I bought it from a Japanese distributor.
Altera_Forum
Honored Contributor I
85 Views

I ordered a THDB_ADA daughter card for the Cyclone III Starter Board directly from Terasic and received it last week. There are no general purpose I/Os on the daughter board. No, you don't need a cable.  

 

I had two problems with the board that took me a few days to resolve. At first, I had no A/D input or D/A output signals. This turned out to be because the POWER ON signal was not being asserted due to a missing pull-up resistor (R59). From the schematic it looks like they may have sent me a board intended for the DE3 although I ordered one for the Cyclone III Starter Board. Once I added this resistor things started working. 

 

However, when I loaded the demo project (top level entity QB3_TOP.v) I found that bit 10 of ADC channel B was stuck at '1'. Here is line 209 of the code: 

 

assign HSMC_TX_N[11] = 1; 

 

It turns out that this signal is bit 10 of the ADC B! Once this line is commented out and the project is recompiled everything seems to be working.  

 

Two other comments: 1) To run the intermod product demo described in the User guide you will need MATLAB. 2) The ADA_Utility implements a very simple two channel waveform generator and free-running digital scope. It works fine, but no source code is provided.
Altera_Forum
Honored Contributor I
85 Views

thanks for the writeup, john.

Altera_Forum
Honored Contributor I
85 Views

Hi All,  

 

I use the Terasic ADA-HSMC daughter card with the Terasic DE3-150 development board and QuartusII/NiosII v9.1 

I want to implement an arbitrary waveform generator using the analog output of the ADA card in a C/C++ environment using the embedded NiosII processor.  

Unfortunately I´m a complete beginner and do not know how to setup the Quartus/SOPC/Nios system and there is no source code available for the ADA demo which comes with the daughter board.  

Could anybody provide me the Quartus/SOPC/Nios project files for a basic example which shows me how to set an analog output of the ADA card in C/C++ ? 

 

Thank you very much!
Altera_Forum
Honored Contributor I
85 Views

 

--- Quote Start ---  

Hi All,  

 

I use the Terasic ADA-HSMC daughter card with the Terasic DE3-150 development board and QuartusII/NiosII v9.1 

I want to implement an arbitrary waveform generator using the analog output of the ADA card in a C/C++ environment using the embedded NiosII processor.  

Unfortunately I´m a complete beginner and do not know how to setup the Quartus/SOPC/Nios system and there is no source code available for the ADA demo which comes with the daughter board.  

Could anybody provide me the Quartus/SOPC/Nios project files for a basic example which shows me how to set an analog output of the ADA card in C/C++ ? 

 

Thank you very much! 

--- Quote End ---  

 

 

Hi there, 

 

I found a link (https://lyle.smu.edu/~devans/2240/lookup-tables.pdf) that might be useful for you to begin with. The lookup table method is simple and straightforward.  

 

Hope it helps, 

 

David from Terasic
Altera_Forum
Honored Contributor I
85 Views

Thank you David! 

This slides are indeed useful, unfortunately they do not help me to set up the Quartus/SOPC/Nios interface.  

 

Regards, Herbert
Altera_Forum
Honored Contributor I
85 Views

Hi Herbert, 

 

Could you help me understand what else that you need to set up the interface when there's a reference design available for DE3+ADA under the directory \Demonstrations\DE3_ADA from the ADA system CD ?  

 

Thanks, 

 

David from Terasic
Altera_Forum
Honored Contributor I
85 Views

Hi David, 

 

the reference design only shows how to interface the ADA card using HDL code in Quartus II. I now want to us the embedded processor NiosII, hence I need to setup a SOPC system. My major concern is about the clocks: As the ADA card is able to, I want to output data with the max rate of 125MSPS. But the default NiosII system clock is only 100MHz. Does this mean by using NiosII I actually sacrifize speed? Can I increase the processors system clock frequency?  

Additionally I want to synchronize the Analog outputs via ADA with the Digital outputs via GPIO0/1. I expect the GPIO is updated with the system clock but the ADA output comes with the 125MHz PLL clock (generated directly in HDL, i.e. Quartus, by PLL Megafunction as shown in the reference design). What do I have to do in the SOPC system to get the 125MHz PLL clock accessible in the NIOS C/C++ code? Or - as the processor is not that fast - can I forward the processor system clock to the ADA card?  

Another approach could be to use Nios to generate a look-up table with all analog and digital data and afterwards output it synchronously via Quartus. How could I store (Nios) and access (Quartus) such a file? 

 

Thanks,  

regards, 

Herbert
Altera_Forum
Honored Contributor I
85 Views

Hi Herbert, 

 

For your first question, my understanding is the Nios II processor and the modules within the system can be driven by different clock pin with different frequency. In that case there shouldn't be any performance issue unless you plan to process the data sampled by the Nios II processor in real time.  

 

For the 2nd part, please let me know if you still have any question based on my reply regarding the first one.  

 

For the last question, I'm not sure if I understand what you are trying to ask exactly. The look-up table generated will be stored (likely in the on-chip memory) and the Nios II processor can send out the data for every clock cycle, though it'll be limited by the processing speed. Alternatively, the look-up table can be stored in the memory (can still be on-chip memory) and the module which handle the DA conversion can act as master to keep polling data from there to achieve maximum performance.  

 

It's been quite a while since I play with this daughter card. I hope the explanation above makes sense to you and you'd find it useful for your application. 

 

David from Terasic
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