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TNT Consultation Request ID [3212] - Sequential Routing for Memory AGILEX

Christopher_Alvarez
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Please see attachment for extra details.

 

Based on this Package Ball Coordinate https://www.intel.com/content/www/us/en/content-details/634867/r31b-r31c-3184b-3184c-package-ball-coordinates-agi-027r31b-agi-022r31b-agf-027r31c-agf-022r31c-devices.html, can you indicate us which pins correspond to Deep Row and which pins correspond to Shallow Row?

Christopher_Alvarez_0-1692915667253.png

 

 

 

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AdzimZM_Intel
Employee
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Hi Chris,


The Shallow Row and Deep Row are assigned to the adjacent bytes in the row.


From my understanding, the pins are grouping in 5 row to group as byte or bytes in column.

For example, the row DR,DP,DM,DN,DL will have at least one byte and the row DK,DJ,DH,DG,DF will have another adjacent bytes.


To alternate adjacent FPGA EMIF ball rows with deep and shallow board via transitions, the row DR,DP,DM,DN,DL will be Shallow Row and DK,DJ,DH,DG,DF will be Deep Row.

Same goes to the other rows for adjacent bytes.


The pin function can be checked in the Pin-Out file for the targeted device.


Regards,

Adzim


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AdzimZM_Intel
Employee
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As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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Christopher_Alvarez
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We tried the method, but it is not clear if our interpretation according to the ball out used is correct or not.

 

What we require is the Ballouts to include details of which pins are shallow or deep row. Can you help us with that information?

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