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Altera_Forum
Honored Contributor I
1,767 Views

TSE MAC, RGMII, Marvell 88E1111 PHY

I am using a Cyclone IV GX dev kit. I have built a qsys system with TSE MAC core. The MDIO connection with the PHY works well. I have enabled the PHY delay options. But I cannot send and receive packet via the on board Marvell 88E1111 Ethernet transceiver.

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Altera_Forum
Honored Contributor I
67 Views

Altera_Forum
Honored Contributor I
67 Views

Thank you. It works now.

Altera_Forum
Honored Contributor I
67 Views

Some bits of transmitted frame is changed when it is received in PC. Why this is happening?

Altera_Forum
Honored Contributor I
67 Views

Can you be more specific? The MAC can overwrite the source MAC address field, it can append a CRC, in will insert padding if the packet is too short, etc. What are you seeing?

Altera_Forum
Honored Contributor I
67 Views

I am sending the following frame from TSE : 

 

0x00, 0x00, // for 32-bit alignment 

0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, // destination address  

0x00, 0x07, 0xED, 0x1B, 0x07, 0xE0, // source address 

0x00, 0x2E, // length or type of the payload data  

0x34,0x34,0x34,0x34,0x34,0x34,0x34,0x34,0x34,0x34, //payload 

0x34,0x34,0x34,0x34,0x34,0x34,0x34,0x34,0x34,0x34, 

0x34,0x34,0x34,0x34,0x34,0x34,0x34,0x34,0x34,0x34, 

0x34,0x34,0x34,0x34,0x34,0x34,0x34,0x34,0x34,0x34, 

0x34,0x34,0x34,0x34,0x34,0x34 

 

 

the received frame is 

 

ffffffffffffff0f0007edbe7107e000e07207e034e3433434 34434334343443433434344343343434434334343443433434 34434334343443433434344343343434434334343443433434 34434334345645. 

 

Can you tell me why received data is changed?
Altera_Forum
Honored Contributor I
67 Views

shuhana - 

 

Your frame is getting corrupted somehow. The first step would be to isolate where the corruption is occurring (in the FPGA or somewhere downstream). I recommend using SignalTap to see what actually goes into and out of the MAC. 

 

Do you have a NIOS in the design? Are you using a DMA? 

 

And how are you capturing the received frame? Are you using wireshark or something equivalent? At this point you just have to follow the packet from where it originates in the FPGA all the way through to where you receive it and find out where things go wrong.
Altera_Forum
Honored Contributor I
67 Views

I tried to use signaltap to debug the system. But I found transmission data always zero.  

 

I hava a NIOS in the design & i am using SGDMA. I am using wireshark to see transmitted packets.  

 

Can you tell me which mac and phy registers i have to initialize so that it works properly?