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TSE MAC and Marvell 88E1111

Altera_Forum
Honored Contributor II
5,179 Views

I'm having trouble to bring up the TSE MAC to Ethernet interface on the Stratix II GX PCIe board. I was able to instantiate a triple speed Ethernet MAC and build logic around it. The loopback at the GMII interface seems work fine. However, I'm not able to send any packet out via the on board Marvell 88E1111 Ethernet transceiver. I suspect I need to program the registers in it via the MDIO. Is there a register map or data sheet of the 88E1111? Or is there anything else I'm missing? 

 

Thanks.
0 Kudos
42 Replies
Altera_Forum
Honored Contributor II
516 Views

Hey guy, 

 

I have successfully make it works before(same dev board, same on-board PHY). A few tricks: 

1. You need to do a RESET on the onboard Marvel PHY when you power up the board (only for this particular onboard PHY, I have no such problem with other Marvel88E111 daughter card or SFP). It is described in the Marvel document as about 10ns second reset (if not mistaken). You can either tie the PHY reset pin to the on board reset button or just use some hard logic to do it. Very odd, powerdown/powerup the board doesn't cleanly reset the PHY. 

(2. to 4. only apply if you are not using the sample application/example design/default TSE driver) 

2. You need to make sure that your MAC, ethermode/speed bit in the command config register represent the mode the PHY is currently working at 

3. Remember to turn off the INTERNAL_LOOPBACK register bits:) 

4. Make sure that you know you are using/not using the 16-bits byte shifting/alignment feature (synthesis/register option in TX/RX_CMD_STAT), 

 

I don't think you need a Marvel Datasheet, all the general settings of any PHY is described in the TSE documentation, unless you need some extended/proprietary settings like turn on the automatic clock adjustment for RGMII interface.
Altera_Forum
Honored Contributor II
516 Views

Thanks. 

 

I somehow got it to work after playing with it for a while. I added some "redundant" initialization sequence in the logic including a reset of the PHY after power up. I suspect that's what made it work as you pointed out. 

 

 

--- Quote Start ---  

Hey guy, 

 

I have successfully make it works before(same dev board, same on-board PHY). A few tricks: 

1. You need to do a RESET on the onboard Marvel PHY when you power up the board (only for this particular onboard PHY, I have no such problem with other Marvel88E111 daughter card or SFP). It is described in the Marvel document as about 10ns second reset (if not mistaken). You can either tie the PHY reset pin to the on board reset button or just use some hard logic to do it. Very odd, powerdown/powerup the board doesn't cleanly reset the PHY. 

(2. to 4. only apply if you are not using the sample application/example design/default TSE driver) 

2. You need to make sure that your MAC, ethermode/speed bit in the command config register represent the mode the PHY is currently working at 

3. Remember to turn off the INTERNAL_LOOPBACK register bits:) 

4. Make sure that you know you are using/not using the 16-bits byte shifting/alignment feature (synthesis/register option in TX/RX_CMD_STAT), 

 

I don't think you need a Marvel Datasheet, all the general settings of any PHY is described in the TSE documentation, unless you need some extended/proprietary settings like turn on the automatic clock adjustment for RGMII interface. 

--- Quote End ---  

Altera_Forum
Honored Contributor II
516 Views

Hi, 

 

I've got a pci express demo board and i want to use GbEthernet communication. 

 

For now, I was able to instantiate TSE MAC and make logic for initialization. with a big sate machine just like in the provided altera test bench. That seem's to work. 

 

But when i send frame on tx fifo interface, nothing come back on the rx fifo interface. And loopback is activate... I think some initializations are missing. I put below my init sequence. could you help me and say me if I wrong or not ? 

 

Init TSE MAC Sequence: 

 

- Read Version (@0x00) and check 0x00000800 

- Write Scratch (@0x01) to 0xAAAAAAAA, readback and check 

- Write Config (@0x02) to 0x040083EB 

 

TX_ENA & RX_ENA = 1 

ETH_SPEED = 1 

PAD_EN = 1 

CRC_FWD & PAUSE_FWD = 1 

PAUSE_IGNORE = 1 

TX_ADDR_INS = 1 

LOOP_ENA = 1 

RX_ERR_DISC = 1 

 

- Write mac_0 & mac_1 (@0x03 & 0x04) to 0x22334450 & 0x0000EE11 (choose MAC: EE1122334450) 

- Write ipg length (@0x17) to 0x0C 

- Write frame length (@0x05) to 1518 (0x5EE) 

- Write pause quanta (@0x06) to 0x0F 

- Write rx_section_empty (@0x07) to 0x00 

- Write rx_section_full, tx_section_empty, tx_section_empty (@0x08, 0x09, 0x0A) to 0x10 

- Write rx_almost_empty, rx_almost_full, tx_almost_empty (@0x0B, 0x0C, 0x0D) to 0x08 

- Write tx_almost_full (@0x0E) to 0x0A 

- Finally, Write mdio_addr0 (@0x0F) to 0x12. 

 

(Sorry for all this details but I wan't you have all the informations to help me!) 

 

 

Did I forget something during init process ? 

Could you help me ? 

 

 

Thanks you very much! 

Fabrice.
Altera_Forum
Honored Contributor II
516 Views

 

--- Quote Start ---  

Hey guy, 

 

I have successfully make it works before(same dev board, same on-board PHY). A few tricks: 

1. You need to do a RESET on the onboard Marvel PHY when you power up the board (only for this particular onboard PHY, I have no such problem with other Marvel88E111 daughter card or SFP). It is described in the Marvel document as about 10ns second reset (if not mistaken). You can either tie the PHY reset pin to the on board reset button or just use some hard logic to do it. Very odd, powerdown/powerup the board doesn't cleanly reset the PHY. 

(2. to 4. only apply if you are not using the sample application/example design/default TSE driver) 

2. You need to make sure that your MAC, ethermode/speed bit in the command config register represent the mode the PHY is currently working at 

3. Remember to turn off the INTERNAL_LOOPBACK register bits:) 

4. Make sure that you know you are using/not using the 16-bits byte shifting/alignment feature (synthesis/register option in TX/RX_CMD_STAT), 

 

I don't think you need a Marvel Datasheet, all the general settings of any PHY is described in the TSE documentation, unless you need some extended/proprietary settings like turn on the automatic clock adjustment for RGMII interface. 

--- Quote End ---  

 

 

 

 

Hi, 

I am using Stratix II gx board and TSE MAC core. Can u please give some more details (logic )on reset logic required to use MARVELL PHY. 

Thanks
Altera_Forum
Honored Contributor II
516 Views

Marvel Data sheet ?  

 

Where did you find that, I have been googling around all over and all I find is the 2 page Product brief.  

 

Any help greatly appreciated! 

 

-Art
Altera_Forum
Honored Contributor II
516 Views

Marvell does not release their datasheets over the web except to users who have a login. 

 

Jake
Altera_Forum
Honored Contributor II
516 Views

It's even worse than that, for the 88E1111 datasheet you need to sign an NDA first.

Altera_Forum
Honored Contributor II
516 Views

how can i configure the registers?

Altera_Forum
Honored Contributor II
516 Views

 

--- Quote Start ---  

Hi, 

I am using Stratix II gx board and TSE MAC core. Can u please give some more details (logic )on reset logic required to use MARVELL PHY. 

Thanks 

--- Quote End ---  

 

 

Did you find how to do the hardware reset? I am looking for the same information
Altera_Forum
Honored Contributor II
516 Views

Find in attached file a screenshot of the original marvell 88e1111 datasheet for its hardware reset sequence. 

 

Works fine on my pcie express board.
Altera_Forum
Honored Contributor II
516 Views

Thank you for this snapshot !!! 

Worth 1000 words.
Altera_Forum
Honored Contributor II
516 Views

Hello, 

I read this discussion but i have question: 

 

have you somebody uClinux running on StratixIII DSP kit with TSE Marvell 88E1111 ethernet chip ?  

 

Everything looks ok, but don´t work ... 

When i use the  

/>ifconfig eth0 hw ether 00:07:ed:ff:4a:d7 

/>ifconfig eth0 192.168.1.234 

/>ifconfig eth0 up 

/>route add default gw 192.168.1.254 

linux report - Trying 10/HALF - in this moment i don`t know what it does ? 

After this i try ping to ip of my pc, it finish by request timeout (and tx led on board don`t blink).  

 

I haven`t problem with reset i think, because examples of webserver (on uC-OSII) work fine and simple socket server too. 

 

Where could be mistake ? 

 

Thank you very much. 

 

Jan Naceradsky, Czech Reublic
Altera_Forum
Honored Contributor II
516 Views

Hello to everybody. 

I'am using cyclone III dev kit, marvell 88e1111 PHY, Triple Speed Ethernet and nios II. 

i want to initialize PHY. 

i try to write code for initializing, but i don't know how to address PHY through the MDIO. 

 

in tse_regs.h there is  

IORD_ALTERA_TSEMAC_MDIO(base, mdio, reg_num)  

IORD_16DIRECT(base, 0x200 + (mdio * 0x80) + (reg_num * sizeof(alt_u32)) ) 

i think i can use it, but what are the parameters? 

base - tse_mac_base? 

mdio - The MDIO address of the PHY device is configured to the value 18 (0x12)?
Altera_Forum
Honored Contributor II
516 Views

The TSE is able to communicate with up to two PHYs through MDIO. You need first to set up the MDIO address of the PHY, with one of those calls:IOWR_ALTERA_TSEMAC_MDIO_ADDR0(base,data) IOWR_ALTERA_TSEMAC_MDIO_ADDR1(base,data)Obviously the first line sets the MDIO address for the PHY number 0 and the second one sets the MDIO address for the PHY number 1. base is tse_mac_base, as you guessed, and data is the MDIO address. 

 

Then you can access the register with one of those calls:IORD_ALTERA_TSEMAC_MDIO(base, mdio, reg_num) IOWR_ALTERA_TSEMAC_MDIO(base, mdio, reg_num, data)The first line reads, the second writes. base is again tse_mac_base, mdio is the PHY number (0 or 1, depending on the call you used to set up the MDIO address), reg_num the MDIO register number, and data is the value to write.
Altera_Forum
Honored Contributor II
516 Views

That's very nice. 

i think that i have access through the mdio to the registers of PHY. 

i also madethehardware reset for my phy and the led of phy blinks. 

and is there any alghorithm of how to send\receive packets, how to config the descriptor to sgdma?
Altera_Forum
Honored Contributor II
516 Views

Do you use an operating system? There are solutions for uCOS, eCOS and Linux to use the TSE core with the NIOS processor.

Altera_Forum
Honored Contributor II
516 Views

I don't use any Os. 

I want to use functions of tse, sgdma to solve this problem. 

besides i use functions from tse drivers of i don't know how to call it.
Altera_Forum
Honored Contributor II
516 Views

Hello to everybody i have another problem: 

i took the example of sending of packet from tse driver, i also formed the descriptor for sgdma_tx, and try to send packet to PC. 

Wireshark shows that packet with right number of bytes, but the packet is corrupted, besides all bytes of data are zero. 

 

but i didn't configure the PHY.  

I make lan adapter in PC to work in duplex 100 mbit and after hard reset PHY connects to it and by auto-negotiation works in duplex and 100 mbit - these parameters meet a demand of my fpga project. 

then I form the packet as an example I took tse_mac_raw_send 

 

Arу there any ideas why it doesn't work? 

or where can i have a look for the control and status registers of PHY? 

I use marvell 88e1111 and there is no datasheet for it. 

can i take another datasheet to PHY with gigabit mode and look for the addresses of registers? 

are there any standatrs for it? 

 

thank for your help.
Altera_Forum
Honored Contributor II
516 Views

Not all registers are standard, unfortunately. 

You can have a look at the TSE driver, it has a few lines configuring the Marvell PHY, you can re-use them in your project. 

As for the empty data packet, it can come from the CPU data cache. Try to flush the data cache before sending the packet, or use the alt_remap_uncached() function to modify your pointer to the memory buffer that you fill in.
Altera_Forum
Honored Contributor II
274 Views

Hi Guys  

I am new to FPGA world and pls correct me if I am wrong.  

 

I brought Stratix II GX PCI development board and trying to compile and run TSE ref design as is. But getting following warnings and Quartus software is not generating any program files.  

 

Warning: Can't generate programming files for project because design file "C:/altera/tse_datapath_reference_design/tse_ref_design/crcgen_altcrc.v" is encrypted. It does not have license file support that allows generation of programming files. 

Warning: Can't generate programming files for project because design file "C:/altera/tse_datapath_reference_design/tse_ref_design/crcchk_altcrc.v" is encrypted. It does not have license file support that allows generation of programming files. 

 

Any Help would be appreciated.
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