FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits

TSE bug with ff_tx_mod = 3?

Altera_Forum
Honored Contributor II
1,058 Views

Hi, did anyone see a problem with the TSE ethernet core when ff_tx_mod = 3? I tested my design, it works fine for ff_tx_mod = 0, 1, 2 but not 3. tcpdump shows 1 or 2 bytes missing. I checked it on SignalTAP and all the signals of TX seem to be OK. Here is my configuration: 

 

board: Cyclone IV GX starter kit 

Protocol: UDP 

Quartus version: 12.1 

 

Thanks, 

Mark
0 Kudos
0 Replies
Reply