Hi all,I got a problem when I tried to connect the TSE MAC to the PHY, some thread said that the enet_gtx_clk should be connected to a 25MHz clock along with the tx_clk_to_the_tse_mac, but my problem is that the enet_gtx_clk is an output and when I tried to connect the clock it comes with an error: Error: Net "gdfx_temp0", which fans out to "enet_gtx_clk", cannot be assigned more than one value Error: Net is fed by "altpllenet_pll:inst4|c1" Error: Net is fed by "nios2_linux_3c120_125mhz_top:inst2|enet_gtx_clk" My board is Cyclone iii 3c120 Anyone can help me with this connection? Or would someone like to give a picture that shows the connection of all the pins of the ethernet in a bdf file? Thanks in advance Jiaqi Yuan
The connection to the clock source is already done in the nios2_linux_3c120_125mhz_top file.Why don't you use nios2_linux_3c120_125mhz_top as your top level file, instead of putting it in a block and reconnect all the pins?
--- Quote Start --- The connection to the clock source is already done in the nios2_linux_3c120_125mhz_top file. Why don't you use nios2_linux_3c120_125mhz_top as your top level file, instead of putting it in a block and reconnect all the pins? --- Quote End --- Hi Daixiwen, it is because i have to connect my scrambler and encoder to the ethernet, could you please tell me how to use the ethernet to connect to my user define block without put it in a bdf file?
Do you need to connect your scrambler/encoder to the (RG)MII interface? In that case you can do as you are doing now, and add your block between nios2_linux_3c120_125mhz_top and the pins, or directly edit nios2_linux_3c120_125mhz_top.v to add your component.If you rather need to work on the decoded packet contents, it would be probably easier to write an Avalon Stream component and add it to the SOPC builder project.
yeah, I want to connect my blocks to the (RG)MII interface, now i have a sopc bsf, nios2_linux_3c120_125mhz bsf and a scrambler bsf in my top level bf file, could you please tell me how to connect them? I try to connect them like the nios2_linux_3c120_125mhz_top.v, while it comes with many errors of the DDIO_OUT WYSIWY primitives.
Another problem is that there are many assignment like this:assign fsa = address_to_the_cfi_flash_64m[25:1] the fsa[24..0] and address_to_the_cfi_flash_64m[25:1] are both output, how can I connect them? And in bdf should i write a new block which made fsa become [25..0] to make it connected?
The errors with DDIO are probably because the RGMII interface uses DDR. You would need to change the SOPC system to have a GMII interface out of the TSE, put your scrambler/encoder, and then do the conversion to RGMII yourself, using DDR inputs/outputs.For the flash address bus, I don't understand your question... address_to_the_cfi_flash_64m[25:1] is an output of the SOPC component, fsa in an output of the design. Just connect them together.
Thanks Daixiwen, now i got a new problem that my transmission data rate is really low, and if i want to speed this, it shows no free buffers for rx, i have read your post thread that there is an accel design for statiex II, but can that be used in the cycloine iii?
bingomickey (http://www.alteraforum.com/forum/member.php?u=26747) can you show your top-level bdf with pinouts?I have some problems during transmission and i don't now where is my mistake, maybe if i can have a look at your workable example i solve my problem.