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Altera_Forum
Honored Contributor I
689 Views

TSE on Stratix III dev. kit - cant fit rx_clk

Has anybody got the Triple speed ethernet to work on the Stratix III Altera dev. kit? 

 

The examples in the kit support package are incompletely constrained and the pinout is lacking assignments. Attempting to fix this gives the error:…. 

 

error: can't place left/right or top/bottom pll "enet_rx_clk_pll:inst| altpll:altpll_component| enet_rx_clk_pll_altpll1:auto_generated| pll1" --  

i/o pin enet_rx_clk (port type inclk of the pll) is assigned to a location which is not connected to port type inclk of any pll on the device. … 

 

I.e. the rx_clk is wired up to an inapproprate pin with respect to have a receiving PLL. I was wondering if anybody has a work-around to this?  

Maybe by not using a receiving PLL, but timing is likely to be complicated to get working in that case.  

Any hints are welcome.
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Altera_Forum
Honored Contributor I
31 Views

I never use a receiving pll on the Ethernet interface. Just connect it to the TSE [R][G]MII interface and ensure it is properly constrained.

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