TSE with the dual SGDMA modules...

[Altera_Forum]

Hi All, 

 I guess I am uncertain how the TX/RX dma's work on the TSE - specifically I am looking to be able to read a few bytes out of a packet, use these bytes to select a memory mapped data structure (one of say 16 port buffers), calculate the start dma position from the buffer's rd/wr pointers, then load the descriptor on the rx dma and pull the trigger.... is this possible while still using the standard BSP generated code?  I am thinking I am missing something - if the tse performs all of this on the fly without allowing the kind of mid-stream sorting of data that I am looking to do, then I will need to change my approach.  Meaning if the tse allocates ram, transfers the data and gives back pointers into memory, then I could use a linked list approach to handling the data... sorting the list into queues and maintaining the lists for egress port transfers (via another SGDMA)...

[Altera_Forum]

You would have to modify the TSE driver to do that, but it should be possible. 

You could prepare a first descriptor for the SGDMA asking to load only the first bytes you require, and then when you decide what to do with the data, create a second descriptor to load the remaining bytes in the packet. You can have a look at the sgdma datasheet (http://www.altera.com/literature/hb/nios2/qts_qii55003.pdf) to see how it works.

[Altera_Forum]

The way that I am transferring data is via a udp socket - I get 2 back-to-back transfers, the first containing a command - (ex a burst data command has a queue number and length). The second transfer is raw data destened to dram. I am using the command transfer decode to build rx descriptors for the sgdma_rx block. Should the transfer simply kick off on the next receipt of data if this was done correctly? I've attached the code if anyone is interested.... 

 Thanks (again) crayner

[Altera_Forum]

Yes, theoretically it should work.