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Terasic Cyclone III embedded development

Altera_Forum
Honored Contributor II
787 Views

Hi 

 

As a total newbie to Altera NIO II development I am having problems compiling/fitting a project supplied with a development kit.  

 

The kit is the Terasic Cyclone III Embedded development kit. The project is:  

 

cycloneiii_3c25_niosii_standard 

 

That I downloaded from the Terasic website as part of the NIOS II embedded evaluation kit, Cyclone III edition V8.0.1.  

 

The version of quartus I am using is 11.0.  

 

After trying to compile the project I am getting the following errors  

 

(first of all Quartus could not find ddr_sdram_phy_ddr_pins.tcl, I then attempted to make a version from a version of the file on the web and hey presto it created itself)…..  

 

 

--- Quote Start ---  

 

Error: ERROR: Open project does not exist. Open an existing project or create a new project. 

 

while executing 

"export_assignments" 

invoked from within 

"if {$make_assignments} { 

set_global_assignment -name FAMILY "Cyclone III" 

set_global_assignment -name DEVICE EP3C25F324C8 

set_global_assignment -na..." 

(file "./ddr_sdram_phy_ddr_pins.tcl" line 42) 

invoked from within 

"source $fn" 

(file "ddr_sdram_phy_ddr_timing.sdc" line 61) 

 

 

--- Quote End ---  

 

 

 

and then at the end of the process… 

 

 

--- Quote Start ---  

 

Error: Can't fit design in device 

Warning: Following 16 pins must use external clamping diodes. 

Info: Pin top_flash_ssram_d[0] uses I/O standard 2.5 V at H3 

Info: Pin top_flash_ssram_d[1] uses I/O standard 2.5 V at D1 

Info: Pin top_flash_ssram_d[2] uses I/O standard 2.5 V at A8 

Info: Pin top_flash_ssram_d[3] uses I/O standard 2.5 V at B8 

Info: Pin top_flash_ssram_d[4] uses I/O standard 2.5 V at B7 

Info: Pin top_flash_ssram_d[5] uses I/O standard 2.5 V at C5 

Info: Pin top_flash_ssram_d[6] uses I/O standard 2.5 V at E8 

Info: Pin top_flash_ssram_d[7] uses I/O standard 2.5 V at A4 

Info: Pin top_flash_ssram_d[8] uses I/O standard 2.5 V at B4 

Info: Pin top_flash_ssram_d[9] uses I/O standard 2.5 V at E7 

Info: Pin top_flash_ssram_d[10] uses I/O standard 2.5 V at A3 

Info: Pin top_flash_ssram_d[11] uses I/O standard 2.5 V at B3 

Info: Pin top_flash_ssram_d[12] uses I/O standard 2.5 V at D5 

Info: Pin top_flash_ssram_d[13] uses I/O standard 2.5 V at B5 

Info: Pin top_flash_ssram_d[14] uses I/O standard 2.5 V at A5 

Info: Pin top_flash_ssram_d[15] uses I/O standard 2.5 V at B6 

Warning: Following 2 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results 

Info: Pin top_mem_clk has a permanently enabled output enable 

Info: Pin top_mem_clk_n has a permanently enabled output enable 

Error: Quartus II Fitter was unsuccessful. 2 errors, 593 warnings 

Error: Peak virtual memory: 314 megabytes 

Error: Processing ended: Tue Jul 05 10:00:26 2011 

Error: Elapsed time: 00:00:43 

Error: Total CPU time (on all processors): 00:00:40 

Error: Quartus II Full Compilation was unsuccessful. 4 errors, 726 warnings 

 

--- Quote End ---  

 

 

How can I find out what is not fitting? As the flow summary says….. 

 

 

--- Quote Start ---  

 

Total combinational functions 7,169 / 24,624 ( 29 % ) Flow Status Flow Failed - Tue Jul 05 10:00:25 2011 

Dedicated logic registers 5,442 / 24,624 ( 22 % ) Quartus II Version 11.0 Build 157 04/27/2011 SJ Web Edition 

Revision Name cycloneIII_3c25_niosII_standard 

Top-level Entity Name cycloneIII_3c25_niosII_standard 

Family Cyclone III 

Device EP3C25F324C8 

Timing Models Final 

Total logic elements 9,229 / 24,624 ( 37 % ) 

Total registers 5530 

Total pins 118 / 216 ( 55 % ) 

Total virtual pins 1 

Total memory bits 72,456 / 608,256 ( 12 % ) 

Embedded Multiplier 9-bit elements 4 / 132 ( 3 % ) 

Total PLLs 2 / 4 ( 50 % ) 

 

--- Quote End ---  

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