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Valued Contributor III
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Terasic DE2: Lot of jitter with default SOF, SRAM timing problems, related?

I don't know if anyone could help me with the following issue: when I load up the default SOF (blue background, ALTERA-logo etc) to my DE2 board, I have a _huge_ amount of jitter on the screen. I mean, scanlines are have noise and are not aligned. Also, with the same board I have problems with SRAM timing. The core I have been debugging is Minimig DE2 port and the system controller part, which uses the SRAM, has random memory errors (in my memory tester code which does write-verify for whole SRAM) - I have relaxed timing etc and the specific ISSI memory part is verified by others to work 100%. This leads me to suspect that a) 50MHz clock is bad, or b) I have voltage jittering. Could anyone tell me where to start looking for the problem? 

 

Mikolas
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Valued Contributor III

Re: Terasic DE2: Lot of jitter with default SOF, SRAM timing problems, related?

 

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This leads me to suspect that a) 50MHz clock is bad, or b) I have voltage jittering. Could anyone tell me where to start looking for the problem? 

 

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These are good ideas. Have you looked at the clock and power supplies with a scope? 

 

Which DE2 do you have; DE2 (original), DE2-70, DE2-115? I have all of these boards, so could double check my board if you have specific questions. 

 

Cheers, 

Dave
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Valued Contributor III

Re: Terasic DE2: Lot of jitter with default SOF, SRAM timing problems, related?

This is the original DE2 with EP2C35. I did take a measure at voltages and they seem to be ok, although I can't do any real measurements due to lack of proper scope. What I also now tested was that I changed the VGA PLL to use the 27MHz oscillator as source. I still have jitter, although less than before. So the problem might be elsewhere (some signal termination?). I really hope the FPGA is not faulty. 

 

Thanks, 

Mikolas
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Valued Contributor III

Re: Terasic DE2: Lot of jitter with default SOF, SRAM timing problems, related?

 

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This is the original DE2 with EP2C35. I did take a measure at voltages and they seem to be ok, although I can't do any real measurements due to lack of proper scope. What I also now tested was that I changed the VGA PLL to use the 27MHz oscillator as source. I still have jitter, although less than before. So the problem might be elsewhere (some signal termination?). I really hope the FPGA is not faulty. 

 

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I'm not sure that 27MHz is the correct frequency for VGA. For example, take a look at 

 

http://en.wikipedia.org/wiki/crystal_oscillator_frequencies 

 

Scroll down to 27.0MHz and you'll see that it is the reference frequency for NTSC/PAL, but scroll down a little further and you'll see that 28.322MHz is a VGA frequency. 

 

Just because Terasic put a 27MHz clock on the board means it is "correct" for all applications. It may be that they expect you to use a PLL to configure the VGA interface. 

 

You might want to do a little searching to see what other VGA examples exist for this board. Hamblen has a book and examples ... 

 

http://users.ece.gatech.edu/~hamblen/de2/ 

 

Cheers, 

Dave
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Valued Contributor III

Re: Terasic DE2: Lot of jitter with default SOF, SRAM timing problems, related?

Yeah, I actually use similar output freqs ("almost" correct since 28.175 clock is not avail on the boards) on my DE2 and DE2-70 and the screen is rock solid on the latter. I have now come to conclusion that there is something going on with the oscillators since the VGA controller clearly has drift on DE2. The PLL generates two clocks for VGA, one for pixel clock and another for OSD framebuffer. These are phase shifted 90 degrees, but for some reason the phase shift and/or pixel/OSD clock seem to jitter (pixels are lit on wrong side of pixel clock or OSD data is not read in on correct phase, take your pick). I need to borrow a scope to see what's going on :-)

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Valued Contributor III

Re: Terasic DE2: Lot of jitter with default SOF, SRAM timing problems, related?

I know this is really late, but after spending weeks trying to solve SRAM problems (and finally finding a solution), I want to post in case it's related to your problem. 

 

Newer DE2 boards have SRAM chips ending with "EDBLL" or similar as opposed to the old ones that were just "BLL" or similar (the "ED" is the important part). 

 

These chips are apparently more sensitive to either spikes or reflections on the control lines, which causes random errors throughout memory when writing to the chip. 

 

To solve the problem, I found that someone recommended setting the line terminations to 25 ohm. I found that it actually works better to set the output current strength to 4mA for all control lines (address, WE_N, OE_N, etc.). It solved all my problems.
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Valued Contributor III

Re: Terasic DE2: Lot of jitter with default SOF, SRAM timing problems, related?

 

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I found that it actually works better to set the output current strength to 4mA for all control lines 

 

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Wow, that was a subtle solution. Were you able to look at those signals with an oscilloscope to see what the ringing on the signals was like before and after you changed the drive setting? 

 

 

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It solved all my problems 

 

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Thanks for posting this info, it will likely help someone in the future. 

 

Cheers, 

Dave
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Highlighted
Valued Contributor III

Re: Terasic DE2: Lot of jitter with default SOF, SRAM timing problems, related?

 

--- Quote Start ---  

I know this is really late, but after spending weeks trying to solve SRAM problems (and finally finding a solution), I want to post in case it's related to your problem. 

 

Newer DE2 boards have SRAM chips ending with "EDBLL" or similar as opposed to the old ones that were just "BLL" or similar (the "ED" is the important part). 

 

These chips are apparently more sensitive to either spikes or reflections on the control lines, which causes random errors throughout memory when writing to the chip. 

 

To solve the problem, I found that someone recommended setting the line terminations to 25 ohm. I found that it actually works better to set the output current strength to 4mA for all control lines (address, WE_N, OE_N, etc.). It solved all my problems. 

--- Quote End ---  

 

 

Hi there, 

 

First of all, I'd like to thank you on behalf of Terasic for the solution. It will certainly help lots of users who are still struggle with the new SRAM on DE2.  

 

I can see that you mentioned the following two solutions here and the 2nd one actually works better than the 1st one, but I have a question in mind before I summarize the whole thing onto our FAQ section - Do you still need to implement the 1st one on top of the 2nd one or the 2nd one along is more than enough to solve the problem ? 

 

1. setting the line terminations to 25 ohm 

2. set the output current strength to 4mA for all control lines (address, WE_N, OE_N, etc.). 

 

Many thanks, 

 

David from Terasic
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Valued Contributor III

Re: Terasic DE2: Lot of jitter with default SOF, SRAM timing problems, related?

The "best solution" should be determined by the interface logic, eg., use a pattern generator to fill and pattern checker to check the SRAM read data, and then sweep the transmit or capture clock to determine the eye pattern to the SRAM. 

 

You can adjust the clock phase using the ALTPLL_RECONFIG component ... I posted an example here 

 

http://www.alteraforum.com/forum/showthread.php?t=46527 

 

Cheers, 

Dave
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