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Altera_Forum
Honored Contributor I
1,005 Views

Terasic TR4-230 Development Board Flash Programming Problem

Hi all, 

I have recently purchased Terasic TR4-230 Development kit and facing a problem with the CFI (common flash interface) flash programming using the PFL (Parallel Flash Interface) IP core. I've got the below points. 

 

----->***** I would like to know if anybody using the same TR4 board, so that we can keep discussing the common problems we face. (As the support for Terasic seems to be too bad direclty from the vendor).***********<--------- 

 

Comming to the present problems 

1. The board has got one USB JTAG blaster connector and two seperate JTAG ISP ports for CPLD (J5) and FPGA (J2) for JTAG external blaster programing. 

2. The USB JTAG connector with auto detect is able to identify only FPGA, and not the 2 CPLDs in the chain. 

3. The CPLD ISP (J5) with external JTAG blaster is able to identify 2 CPLDs and I am able to program the CPLDs 

4. The FPGA ISP (J2) with external JTAG blaster is not able to identify any device in the auto detect mode. 

 

My question is whether all the CPLDs and FPGA are not in the common JTAG chain?  

And to program the Flash (CFI), where I have to put the PFL Ip core, i.e in CPLD or FPGA? and where to attach the Flash device? 

The TR4 manual show the flash programing through NIOS flow, but I don't have NIOS license. 

 

Plz guide me how to program the flash for FPGA configuration. Thanks in advance :) 

 

Srikanth 

India
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2 Replies
Altera_Forum
Honored Contributor I
37 Views

You can use Nios without a license but only if the board is connected via jtag, as it would be when programming flash.

Altera_Forum
Honored Contributor I
37 Views

Thank you Galfonz for you reply. 

For programming the Flash, I feel NIOS is not required. I' got the solution after a bit of struggle and I could able to program the flash by putting the PFL ip in CPLD and upgrading the Quartus 14.0 to Quartus 15.1 s/w. There is a bug in 14.0 which is giving flash programing error with PFL IP core, which I found out through search.  

 

Regards 

Srikanth
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