I will use the IP"Avalon-ST Dual clock FIFO Intel FPGA IP " in Quartus PRO 18.1.
Could you help to check how to config these parameters? I found same hints in datasheet, but don't understand total.
Below are details on how to configure the FIFO Parameter. These will be updated in the future Quartus version.
Data Width: Width of data going into/out from the FIFO.
Chanel Width: The width of the channel signal. 0 means that the signal is omitted.
Use Packets: If enabled, the packet signals will be used. Parameter =1 when enabled, disable = 0
Prevent Underflow: Enable or disable underflow. Parameter =1 when enabled, disable = 0
Showahead: When showahead=1, FIFO treats ready ports as read acknowledge that automatically outputs the first valid data word when FIFO is not empty, without asserting the ready signal. When showahead =0, FIFO treats the ready port as read request that only performs read operation and outputs data when the port is asserted.