The fpgainfo phy showing a port is flapping state

[Ravishankar]

fpgainfo phy | grep -e "^PCIe" -e "^Port"

PCIe s:b:d.f         : 0000:8a:00.0

Ports Num           : 01

Port0 25G           : Up

Port1 25G           : Down <<<<<<<<<<<<<<<<<<<<<<<<<<<<

PCIe s:b:d.f         : 0000:1c:00.0

Ports Num           : 01

Port0 25G           : Up

Port1 25G           : Up

fpgainfo phy | grep -e "^PCIe" -e "^Port"

PCIe s:b:d.f         : 0000:8a:00.0

Ports Num           : 01

Port0 25G           : Up

Port1 25G           : Up

PCIe s:b:d.f         : 0000:1c:00.0

Ports Num           : 01

Port0 25G           : Up

Port1 25G           : Up

[SengKok_L_Intel]

Hi,

In order to better assist you, would you please let us know which PAC card that you are using? Is this N3000 or D5005?

Besides, what type of server you are using for this PAC card? How many PAC cards in that server?

Regards -SK

[Ravishankar]

Thi is N3000 PAC Card. We are using Quanta server.

There are two PAC card in this server.

[Ravishankar]

Please find the detailed FPGAINFO output-

FPGA port mapping

[root@<Compute_Name> ~]# fpgainfo phy | grep -e "^PCIe" -e "^Port"

PCIe s:b:d.f         : 0000:8a:00.0

Ports Num           : 01

Port0 25G           : Up  << vc_sriov1

Port1 25G           : Up  << vc_sriov3

PCIe s:b:d.f         : 0000:1c:00.0

Ports Num           : 01

Port0 25G           : Up  << vc_sriov0

Port1 25G           : Down << vc_sriov2

[root@<Compute_Name> ~]#

Check FPGA ports status with "fpgainfo phy" command.

[root@<Compute_Name> ~]# fpgainfo phy

Board Management Controller, MAX10 NIOS FW version D.1.0.12

Board Management Controller, MAX10 Build version D.1.0.12

//****** PHY ******//

Object Id           : 0xEE00001

PCIe s:b:d.f         : 0000:8a:00.0

Device Id           : 0x0b30

Numa Node           : 1

Ports Num           : 01

Bitstream Id         : 0x2230120056D577

Bitstream Version       : 0.2.2

Pr Interface Id        : cf9b1c50-37c9-45e9-8030-f921b17d2b3a

//****** PHY GROUP 0 ******//

Direction           : Line side

Speed             : 25 Gbps

Number of PHYs        : 2

//****** PHY GROUP 1 ******//

Direction           : Fortville side

Speed             : 40 Gbps

Number of PHYs        : 2

//****** PKVL ******//

Port0 25G           : Up

Port1 25G           : Down

Parkvale A Version      : 101c.1064

Parkvale B Version      : 101c.1064

Board Management Controller, MAX10 NIOS FW version D.1.0.12

Board Management Controller, MAX10 Build version D.1.0.12

//****** PHY ******//

Object Id           : 0xEE00000

PCIe s:b:d.f         : 0000:1c:00.0

Device Id           : 0x0b30

Numa Node           : 0

Ports Num           : 01

Bitstream Id         : 0x2230120056D577

Bitstream Version       : 0.2.2

Pr Interface Id        : cf9b1c50-37c9-45e9-8030-f921b17d2b3a

//****** PHY GROUP 0 ******//

Direction           : Line side

Speed             : 25 Gbps

Number of PHYs        : 2

//****** PHY GROUP 1 ******//

Direction           : Fortville side

Speed             : 40 Gbps

Number of PHYs        : 2

//****** PKVL ******//

Port0 25G           : Up

Port1 25G           : Up

Parkvale A Version      : 101c.1064

Parkvale B Version      : 101c.1064

[root@<Compute_Name> ~]#

[JonWay_C_Intel]

Hi @Ravishankar​ I have sent you a private message.

[JonWay_C_Intel]

Hi @Ravishankar​ 

Does this happen to SRIOV use case only?

Could you explain the steps you took to replicate the issue?

[Ravishankar]

Yes this happends to only SRIOV port on the FPGA card. This is seen randomly in the Server having this FPGA card.

What are other logs that we can see to get more details of this issue?

[JonWay_C_Intel]

Hi @Ravishankar​ 

Sorry for the delayed response. May I know if this issue has been resolved?

If not, would you send me the steps to reproduce the issue.