The target hardware identity couldn't be verified.

[Balerion]

Hi,

I have been trying to debug a simple hello world app in Agilex-7 SoC Dev-Kit. However, I'm not able to connect the board, download the helloWorld.axf file and debug it. I attached the error that IDE gives me to this post. It says "The target hardware identity couldn't be verified. Please check that the target being connected to is of type Agilex-7 SoC". Could you please help me about that?

Best regards,

Balerion

[Gokulraj]

Hi Balerion,

Do you found any solution..

[Balerion]

Hi Gokulraj,
I solved this issue. I found out that the HPS is not seen in Jtag chain by the Quartus Programmer. I made some research about it and found that it needs a FSBL (First-Stage Bootloader) to boot up which is actually an SPL (Secondary Program Loader). It is a .hex file. However, I couldn't build and generate it on my own. I found a prebuild one for DK-SI-AGF014EA. I didn't expect it to work on my board which is DK-DEV-AGF014EA, but it worked. Then, I merged that .hex file with .sof and created a .jic file and embed it to the QSPI chip on the board. Then, I reboot the device and HPS is detected in jtag chain, and the problem is solved in ARM DS too. It is able to detect the board and HPS now. After all, I am able to run simple hello world app at OCRAM and SDRAM but don't forget that a .scat file which is a linker file is needed to download the code to the board.
Best Regards,
Balerion

[Gokulraj]

Dear Balerion,

I have tried to build the .hex file by using the below link.

https://www.rocketboards.org/foswiki/Documentation/AgilexSoCGSRD#Building_the_GSRD_for_the_DK_45SI_45AGF014EA_Version

But i'm unable to build,due to issue in OUTPUT Directory and make file,I have attache the error image for your reference.Could you help me in this.

Thanks ,

Gokulraj

[Balerion]

Hi Gokulraj,

I have tried with prebuild files. Can you also try with that from Index of /2024.04/gsrd/agilex7_dk_si_agf014ea_gsrd/ (rocketboards.org)

Balerion

[Gokulraj]

Dear Balerion,

While merging the .sof and .hex(u-boot-spl-dtb) file Quartus prime throw error as size of file exceeds memory capacity and i'm using .sof(Agilex_SOM.sof) file given by Terasic. Also i tried of configuring FPGA by using  quartus_pgm command in terminal but this one also throw error as device agfb014r24b2e2v is not supported.

 I have attached the error image.Do you face any of this errors.which part i'm missing,could you guide me.

Thanks

Gokulraj 

[Fakhrul]

Hi Balerion,

I'm glad to hear your issue has been solved. BTW, we sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum cases, along with others, did not get through as intended. As a result, we have a backlog of cases that we are currently working through one by one.

Please be assured that we are doing everything we can to resolve this issue as quickly as possible. However, this process will take some time, and we kindly ask for your patience and understanding during this period. The cases will be attended by AE shortly.

We appreciate your patience and understanding, and we are committed to providing you with the best support possible.

Thank you for your understanding.