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Altera_Forum
Honored Contributor I
747 Views

TimeQuest Specification for DE2i-150 board

Hi, 

 

I'm starting to use the DE2i-150 dev board for a course at my school. 

 

I'm currently working on interfacing with the on-board SSRAM, and am starting to wonder about timing constraints. 

 

Is there an example SDC file that I can use with TimeQuest in order to verify the timing constraints on the SSRAM ports? Also, is there a reference to the board-delays that I should use, based on the PCB design during the timing analysis? 

 

I saw some references online to generating a delayed PLL clock signal for the SSRAM, and I'm hoping that TimeQuest can push me in the correct direction for setting the delay.  

 

Here's the current SDC that I've worked out, and it might be correct, based on the SSRAM documentation (I'm also hoping that TerasIC has published an example that I could just use which factors in board delays....) 

 

derive_pll_clocks 

 

 

create_generated_clock -name ssram_clock -source  

[get_pins pll|altpll_component|auto_generated|pll1|clk[0]] [get_ports SSRAM_CLK] 

 

 

set ssram_outs [get_ports {SSRAM*}]  

set ssram_outs [add_to_collection $ssram_outs [get_ports FS*]]# setup time (Tclk - setup) = 1.4ns 

set_output_delay -clock [get_clocks ssram_clock] -max 1.4 $ssram_outs# hold time (0.5 ns) 

set_output_delay -clock [get_clocks ssram_clock] -min 0.5 $ssram_outs -add_delay
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3 Replies
Altera_Forum
Honored Contributor I
21 Views

Download the system CD from the Terasic web site. It should have complete source for examples that exercise everything on the board.

Altera_Forum
Honored Contributor I
21 Views

 

--- Quote Start ---  

Download the system CD from the Terasic web site. It should have complete source for examples that exercise everything on the board. 

--- Quote End ---  

 

 

Thanks for the reply. I have searched the CD, and found some examples, but not the ones that I want. 

 

Looking at the SDC files, I see some clock constraints added to various ports (for ethernet, VGA, and PCIe), but I was not able to find any examples of either setup/hold time constraints or board delays. 

 

Do I need to look in files other than SDC files?
Altera_Forum
Honored Contributor I
21 Views

It looks like another user has run into similar issues with a different board: http://www.alteraforum.com/forum/showthread.php?t=26955 

 

But, there was no answer to that thread.
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