Hi,
I'm starting to use the DE2i-150 dev board for a course at my school.
I'm currently working on interfacing with the on-board SSRAM, and am starting to wonder about timing constraints.
Is there an example SDC file that I can use with TimeQuest in order to verify the timing constraints on the SSRAM ports? Also, is there a reference to the board-delays that I should use, based on the PCB design during the timing analysis?
I saw some references online to generating a delayed PLL clock signal for the SSRAM, and I'm hoping that TimeQuest can push me in the correct direction for setting the delay.
Here's the current SDC that I've worked out, and it might be correct, based on the SSRAM documentation (I'm also hoping that TerasIC has published an example that I could just use which factors in board delays....)
derive_pll_clocks
create_generated_clock -name ssram_clock -source
[get_pins pll|altpll_component|auto_generated|pll1|clk[0]] [get_ports SSRAM_CLK]
set ssram_outs [get_ports {SSRAM*}]
set ssram_outs [add_to_collection $ssram_outs [get_ports FS*]]# setup time (Tclk - setup) = 1.4ns
set_output_delay -clock [get_clocks ssram_clock] -max 1.4 $ssram_outs# hold time (0.5 ns)
set_output_delay -clock [get_clocks ssram_clock] -min 0.5 $ssram_outs -add_delay
