I am having a question on HPS side memory controller.
The timing analyzer complain the timing issue of HPS memory DQS signals.
But from the message I received, all the HPS peripherals like USB, I2C clocks and memory controller need not doing any timing constraint as they are hard coded.
And Quartus will handle it automatically.
Is it correct?
I don't care any timing complaints on HPS side.
Please let me know.
Firstly, may I know which Quartus version and SoC device are you currently working on?
Is it possible for you to share the message that you are seeing or screenshot? Which ever is easy for you, so that I can check what type of message is to be ignored.
Yes, timing constraints are fixed for both dedicated HPS I/Os for Cyclone V SoC and Arria 10 SoC you do not need to define it.
You may refer below for more information regarding the timing constraints on our SoC devices (refer Table 7 on both links )
Cyclone V SoC:
Arria 10 SoC:
I believe the screenshot are the timing compilation report.
Warnings report can be seen at the bottom of the screen, e.g:
Warning (332174): .....
Warning (332174): ....