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Timing violation TRDB_D5M_CD_v1.0 and DE_TV demos

Altera_Forum
Honored Contributor II
‎06-13-2010 09:00 PM
879 Views

Hello 

 

I has create a symbol with the toplevel from the 5 megapixel demo project TRDB_D5M_CD_v1.0 for DE2 Board. 

But when I insert the symbol in a block diagram and sets the Input/Output, after the synthese I have timing violation and the VGA-Monitor d'ont display a perfect image. 

The same problem I have with the video demo on the Terasic CD DE2_TV. 

 

In the attachment you find the two demo project, could you try on your system? Maybe your found the problem.... 

 

For any tips I thanks....
multiple-attachments.zip
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Altera_Forum
Honored Contributor II
‎03-02-2011 09:49 PM
177 Views

I am having similar problems, the design compiles but fails several timing analysis tests. Has anyone solved these problems?

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