We are trying to generate bitfile for FPGA with our openCL code with Profile switch enabled.
The command used is "aoc -v device/simram.cl -o bin/simram.aocx -report - profile" .
Instead of generating the bitfile, the tool crashes everytime.
Kindly Suggest if we are missing anything here. Need Help here in generating Bitfile with Profile switch enabled.
Yes, we still need help here as we are still facing the same issue.
Regarding "Run the "- profile" as "-profile" " , yes we had already tried with "-profile" the space in the query got added by mistake.
Regarding "Compile whitout a the "-profile" " , yes, we have compiled without the "-profile" itself.
Even after this, we are still seeing the issue.
Further to add, what we observe is-
We are able to run -profile with less (PE = 32, 64) configuration but when we are increasing our configuration (PE = 128/256) the resources utilized are exceeding the FPGA size.
Is there any way to optimize the profile logic so that we can fit in the given FPGA. Using Stratix 10MX where 80% is utilized by our code (with maximum config).
- "May I know the your openCL version?"
The openCL version we are using is 21.1
- "Other than that, where do you specify your PE configuration value?"
The PE configuration value is defined in the file “opencl_defines.h” as a macro/fixed value. Hence, If we want to change the PE value, we modify this macro and again we need to recompile and generate the “.aocx” file.
You can check with this document for optimizing related info.
Can you share with me your compilation files? I would like to try compile it on my side if possible.
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