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Transceiver Native PHY Intel Cyclone 10 FPGA IP

Suhas_1994
Beginner
611 Views

Hello,

 

I am trying to generate the Transceiver Native PHY using Quartus. The design gets generated successfully.  When I try to compile the design, I'm getting the error which is attached below.

 

Can someone please help me in fixing the issue??

 

Thanks in advance

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CheePin_C_Intel
Employee
602 Views

Hi,


As I understand it, you have some inquiries related to the Fitter error. As I look at your screenshot, it seems like you are trying to connect the transceiver pins to general purpose IO. For your information, the transceiver pins have dedicated location in a device. I would recommend you to remove all the pin assignment and allow the Fitter to perform autofit. You then refer to the optimal location assigned by Fitter.


Please let me know if there is any concern. Thank you.


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Suhas_1994
Beginner
587 Views

Hello,

 

After generating the design, there are no pin assignments done. When compiled, it still shows the same error as before.

Can you please help me with this?? 

 

Thanks in advance.

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CheePin_C_Intel
Employee
576 Views

Hi,


Thanks for your update. Would you mind to share a simple test design which could replicate you observation? I would like to further look into it. Thank you.


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CheePin_C_Intel
Employee
565 Views

Hi,


Just to follow with you on the simple test design for replication. Thank you.


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CheePin_C_Intel
Employee
563 Views

Hi,


As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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