Try to program FPGA from flash memory, I build a PFL IP project with MAX II CPLD chip and generate .pof. While after CPLD programming, the unexpected errors in JTAG server happened,code 12,84,44.

[sFu001]

The development board is "stratix IV GX FPGA development board,530 edition". As the description in the reference manual, I program the CPLD PFL .pof into MAX II CPLD and it can configure the FPGA from flash memory. Before programming, the programmer can setup hardware while after programming, the JTAG errors happen and no hardware detect. After power up again, I can find USB-blaster and auto detect the device. However, the JTAG server error happened again after auto detect. I assume it's because of the .pof file in CPLD while I cannot erase it because of the JTAG server issue.

[JohnT_Intel]

Hi,

Could you provide me your SW4 and SW6 setting? May I know are you using external USB-Blaster or Internal USB-Blaster?

[sFu001]

SW4.1 OFF, SW4.2 OFF, SW4.3 ON, SW4.4 OFF, SW4.5 ON, SW4.6 ON, SW4.7 ON, SW4.8 OFF. SW6.1 OFF, SW6.2 ON, SW6.3 ON, SW6.4 ON. I'm using embedded USB-Blaster. The SW4&SW6 settings have not changed. Before the programming from flash using CPLD, I can program over embedded USB-Blaster. The file programmed into CPLD may result in JTAG issue after auto detect. I'm confused how can I erase CPLD in the condition no hardware setup in programmer. It's quite urgent. Thanks!

[JohnT_Intel]

Hi,

Is it possible for you to use external USB-Blaster? I suspect that when you erase the CPLD then it somehow cause the embedded blaster to be disabled.

[sFu001]

Could you introduce how to program FPGA & erase CPLD using external USB-Blaster? Need extra specific hardware device and software environment?

[JohnT_Intel]

Hi,

You will need to purchase the cable (https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/download-cables.html). Everything else will be the same.

[sFu001]

Got it! Thanks a lot.

[JohnT_Intel]

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