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Altera_Forum
Honored Contributor I
1,043 Views

Two Master RAM Access

Hi i m using NEEK and i m trying to get a hugh amount of Data from an Verilogfile to the NiosII  

 

Now i tried to include an Avalon MM Master (Template for Burst Writing) to the SoPC that connects with the DDR-RAM, and the NIOS II Processor also connects to the DDR-RAM 

Templates i use : http://www.altera.com/support/examples/nios2/exm-avalon-mm.html?gsa_pos=2&wt.oss_r=1&wt.oss=avalon%2... 

 

now if i start the sof file the Signaltap shows my set options, and they seem to be ok. but when i start on NIOS IDE to programm anything it always tells: 

Pausing target processor: OK 

Initializing CPU cache (if present) 

OK 

 

Downloading 02000000 ( 0%) 

Downloaded 43KB in 0.7s (61.4KB/s) 

 

Verifying 02000000 ( 0%) 

Verified OK  

Leaving target processor paused 

 

 

i only read with  

 

a = IORD_32DIRECT(ALTMEMDDR_0_BASE,0); 

printf("%d",a); 

 

ALTMEMDDR_0_BASE is the Base Adress of the DDR RAM in the system.h 

 

can anyone tell me what i have to do to access the DDR RAM with the NIOS II CPU as Master and via the Template Master that i controll via HDL??? 

 

Thx for ur help 

René Gärtner
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11 Replies
Altera_Forum
Honored Contributor I
114 Views

There is nothing wrong in the messages displayed by the IDE. What did you expect? 

If your application isn't running, you can check first if it comes from your HDL or not. Something you can try is to recompile everything with your module disabled, and then see if it runs. If it is your component that freezes the system, it could be a good idea to use signaltap probes on its ports to see what it is doing. 

 

Did you properly constrain your project and does it meet all timing requirements?
Altera_Forum
Honored Contributor I
114 Views

i think that message appears cause the HDL is accessing the DDR-RAM 

 

that is also the exception Vector of the NIOS II 

 

i think thats why i can t upload it 

 

my question is what i have to do that i can access the RAM with 2 Masters 

 

i want that one Master (the HDL one) writes about 185000 x 24 Bit Data on the DDR-RAM 

after that the master should free the DDR ... dunno how that works 

and the NIOS II SoftCore should read from the DDR-RAM the 185000 x 24 Bit Data 

 

edit: 

The Adress of the DDR-RAM is 0x02000000
Altera_Forum
Honored Contributor I
114 Views

heres a pic of my SOPC and of the Blockdiagram 

 

the Code in the own block is simple and not really big ... dunno if its correct but it saves something to the DDR-RAM 

 

reg myState; reg Data; reg done; reg counter; assign Data = {8'hAF}; always@(posedge CLK50) begin if(!done) begin controllFIXED <= 0; controllWriteBase <= 32'h02000000; controllWriteLenght <= 32'h4; userBufferInput<= Data; if(myState == 0) begin controllGO<= 1; end else begin controllGO<= 0; end myState <= myState +1; if(!userBufferFull) begin userWriteBuffertoTheMaster<=1; end else begin userWriteBuffertoTheMaster<=0; end if (controllDONE) begin myState <= 0; counter <= counter +1; end if (counter >= 2000) done <= 1; end end  

 

http://www2.pic-upload.de/thumb/26.02.10/b8km8hhza9w.jpg (http://www.pic-upload.de/view-4744440/sopc-2-master.jpg.html

(http://www.pic-upload.de/view-4744440/sopc-2-master.jpg.html)http://www2.pic-upload.de/thumb/26.02.10/vbp6o9q1qbjb.jpg (http://www.pic-upload.de/view-4744478/sopc-2-master-blocks.jpg.html)
Altera_Forum
Honored Contributor I
114 Views

I'm not familiar with the template and how it works, but you should connect a Signaltap probe to the ports on your HDL to check if it isn't writing continuously. If it is, it will prevent the CPU from working properly. 

Another reason could be that you are overwriting the reset or exceptions vectors in the DDR, making the CPU crash.
Altera_Forum
Honored Contributor I
114 Views

I forgot to mention... you should give reset values for all your registers. If you don't your component can start in a strange state at power up. 

Resetting your HDL with the same signal than the one resetting the SOPC system is recommended.
Altera_Forum
Honored Contributor I
114 Views

mhh not that easy with that signaltap to get my signals -.- 

 

i ll try the reset conditions 

 

but what i don t understand is that it is blocked by my HDL cause after 2000 Writes it shouldn t access the ddr anymore -.-
Altera_Forum
Honored Contributor I
114 Views

I'm not sure I understand everything you are doing in your code. If mystate is 0 at the time that the counter reaches 2000, controllGO will stay at 1 forever. 

 

Where are your reset and exception vectors?
Altera_Forum
Honored Contributor I
114 Views

oh ur right 

 

i really should set ControllGo to 0 then... 

 

u mean of my NIOS II ? the reset Vector is set to DDR-RAM and the exception to the On-Chip Memory
Altera_Forum
Honored Contributor I
114 Views

So your HDL is overwriting the startup code, which isn't good... Is you application also located on the DDR? 

The best way to do it would be to have your software allocate a memory block and give its address to your HDL through a register (you'll need an Avalon slave interface for that).
Altera_Forum
Honored Contributor I
114 Views

hmm i thought i can access cause of that Master Modul with both Componentens, the HDL over the Master Modul and the NIOS II CPU.... mhh thought SoPC-Builder generates an Aribitation for both ... mhhh

Altera_Forum
Honored Contributor I
114 Views

It isn't the same thing. SOPC builder will do the arbitration so that the CPU and the HDL will share access to the RAM. But you still need to tell your HDL where to put the data.

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