HiI am trying to use the CII_Starter_USB_API_v1 demonstration supplied with the Cyclone II FPGA starter kit. This lets you send a file to flash or SDRam, and read back a file from Flash or SDRam. The problem is that the file read back is different each time it is read. Does anyone know if there is an updated version of this demonstration (I can't find one) or can anyone give me a heads up on how to fix this problem. Alternatively is there another ready made free USB driver interface that I could use with the CII? Thanks Ian
Thank you for your reply.1- Regarding the input clock frequency “fHSCLK”, from the previous mentioned tables, the lowest value of its maximum is 155.5MHZ. So, the lowest value of the maximum fHSCLK for the device (EP2C20Q240C8N) is 155.5 MHZ. Kindly confirm. Kindly confirm if it is applicable to use the device (EP2C20Q240C8N) in my design with 125 MHZ taking into consideration that, 150 MHZ will be generated internal the FPGA from the used 125 MHZ). Reference to “Cyclone II Device Family Data Sheet” page 2–53,which stated that: the Cyclone II devices can transmit and receive data through LVDS signals at a data rate of up to 640 Mbps and 805 Mbps. Can I implement the 1G Ethernet using the “EP2C20Q240C8N” ?