Unable to merge three 9x9 multipliers into a single DSP

[Yogesh]

In cyclone V devices each DSP device will have three 9x9 multipliers as given in the below document (page 3-10)

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v2.pdf

I am unable to merge three 9x9 from a single DSP. If I use three lpm_mult (each performing 8x8 multiplication ), quartus fitter will use 3 separate DSPs instead of a single DSP.

Consider three 8x8 multiplications :​

A1[7:0] x B1 [7:0] = out[15:0] -->first 9x9

A2[7:0] x B2[7:0] = out2[15:0] -->second 9x9

​A3[7:0] x B3 [7:0] = out3[15:0] -->third 9x9

I want to implement above 3 lines using a single DSP(with latency of 3 clock cycles). ​

Please provide me a simple code/example design to do so.

​thankyou

Regards

Yogesh​

[CheePin_C_Intel]

Hi,

As I understand it, this seems to be similar to the case 04581992. For your information, I have shared a simple test design using LogicLock to for 3 8x8 multiplier into a single DSP block for your reference. Please feel free to refer to it.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[CheePin_C_Intel]

Hi,

I believe you might be aware of it. Just would like to share with you that you can also make use of the existing DSP feature multiplier HDL templates in Quartus to ease your coding. For example, in the workaround that I previously discuss, you may refer to the Insert Template -> Verilog HDL -> Full Designs -> Arithmetic -> DSP Features -> DSP Features for 28-nm Device -> "Multiplier with One Operand from Pre-Adder" for example code. You may set input C = 0x1 to leverage the pre-adder. Hopefully this will be helpful.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin