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jrodr29
Novice
554 Views

Use UART controller from FPGA in CycloneV, DS1-Soc board

I'm looking forward for simple design flow to implement serial interface between FPGA and Host PC.

 

I'm aware I can connect HPS pins to FPGA to get uart_rx and uart_tx signals. Platform editor allows to work in two ways for this: (1) connect UART controller pins to FPGA (2) IO loaning.

 

In both cases its not clear how to connect the input and output signals added to the hps component instantiation, to the FPGA resources and be able to access them without incurring into synthesis error. Then:

 

(*) How to connect exported HPS pins to the top level module IO ports and internal signals?

 

(*) Regarding the preloader configuration, is it a must when using io loaning? Will GPIO selection in the Pin Multiplexer help to simplify the setup vs IO loan?

(*) Finally, accessing the UART through the AXI bridge may also work, can that setup function without starting up ARM processor, specifically, may the HPS work standalone?

 

Many thanks in advance.

 

 

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3 Replies
a_x_h_75
New Contributor III
49 Views

AN706 talks you through configuring the HPS so that HPS pins are exposed to the FPGA fabric.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/soc/e...

 

Cheers,

Alex

jrodr29
Novice
49 Views

Hi Alex, thanks for your reply.

  • I've been following the application note without success. I can expose HPS pins as indicated there (by assigning FPGA in the Peripheral Pin configuration in Platform designer and exporting them). I also connected them in the hps instantiation in the top level design and added the required AL_IOBUF instances.
  • However given the application note is for another device, I cannot figure out how to proceed to the PAD connection. I.e when exporting uart0_tx and uart0_rx, quartus asks to connect them to a top level pin, and after that I couldn't find a way to apply proper pin assignment. Connecting them to B25 and C25 (the HPS pins associated to those signals in the board datasheet) quartus will report error in pin assignment.

 

 

Additionally,

 

jrodr29
Novice
49 Views

Here is helpful information regarding connection:

https://forums.intel.com/s/question/0D50P00003yyQXbSAM/how-to-let-fpga-get-access-to-hps-pins?t=1557...

 

Key it to use loan 49 and loan 50 on this board (instead of 60 and 61 which would be the direct understanding in Platform Designer gui)

 

 

 

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