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4953 Discussions

Using 644.53125 MHz clock on Stratix V Dev Board

M3511
Novice
432 Views

Hi,

I need to use the 644.53125 MHz clock on the Stratix V development board.  Do I just need to connect to pins AB34/AB35? Or do I also need to set it to that particular frequency? Not completely clear on whether the U46 programmable LVDS quad-clock will already have 644.53125MHz on the pins when first powered up.

 

Thank you

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1 Solution
AR_A_Intel
Employee
319 Views

Hi

 

Thanks for update. Based on my understanding, dev kit board already pre-programed with certain default clock frequency value. The default clock frequency value can be checked via either user guide doc or from schematic. U46 CLK1 output 644.5313MHz by default this mean clock generator chip (for example U46) will generate clk1 output = 644.5313MHz directly. No need to set anything.


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8 Replies
M3511
Novice
420 Views

Also, does the QSFP breakout cable need to be active optical instead of passive copper?

AR_A_Intel
Employee
368 Views

Hello

 

Welcome to INTEL forum. May we know, is this the board that you’re referring to?

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-st...


AR_A_Intel
Employee
320 Views

Hi

 

Thanks for update. Based on my understanding, dev kit board already pre-programed with certain default clock frequency value. The default clock frequency value can be checked via either user guide doc or from schematic. U46 CLK1 output 644.5313MHz by default this mean clock generator chip (for example U46) will generate clk1 output = 644.5313MHz directly. No need to set anything.


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M3511
Novice
302 Views

Thank you. I believe you are right.

Also, does it matter whether the QSFP breakout cable is active optical or passive copper?

M3511
Novice
232 Views

Does it matter whether the QSFP breakout cable is active optical or passive copper?

AR_A_Intel
Employee
191 Views

Hi

 

Based on m understanding, it shouldn’t matter and it depends on whether you using it with Intel FPGA IP or your own IP.

If you are using Intel FPGA IP then you could check the IP user guide doc for further clarification.


AR_A_Intel
Employee
153 Views

Thanks for your update. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


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